MPC961CAC IDT, Integrated Device Technology Inc, MPC961CAC Datasheet - Page 9

• Manufacturer Part Number: MPC961CAC
• Description: IC BUFFER ZD 1:18 PLL 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Zero Delay Bufferr

Specifications of MPC961CAC

• Pll: Yes
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:17
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: No/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MPC961C Data Sheet
MPC961C REVISION 5 AUGUST 17, 2009
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
Figure 12. Output-to-Output Skew t
Figure 14. Output Duty Cycle (DC)
Figure 16. Cycle-to-Cycle Jitter
t
T
P
N
T
T
0
N+1
DC = t
t
SK(O)
P
/T
0
T
x 100%
JIT(CC)
t
F
= |T
Figure 18. Output Transition Time Test
N
SK(O)
–T
N+1
V
V
GND
CC
CC
V
V
GND
V
V
GND
|
CC
CC
CC
CC
÷ 2
÷ 2
÷ 2
Reference
t
R
The deviation in t
in a random sample of cycles
CCLK
FB_IN
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles
9
V
CC
CCLK
FB_IN
Figure 13. Propagation Delay (t
0.55
=3.3 V
2.4
V
CC
T
0
0
1.8 V
0.6 V
=2.5 V
Figure 17. Period Jitter
for a controlled edge with respect to a t
offset) Test Reference
t
(∅)
Figure 15. I/O Jitter
T
T
JIT(∅)
JIT(PER)
PD
©2009 Integrated Device Technology, Inc.
LOW VOLTAGE ZERO DELAY BUFFER
= |T
, static phase
= |T
0
–T
N
–1/f
1
mean|
0
|
V
V
GND
V
V
GND
CC
CC
CC
CC
0
mean
÷ 2
÷ 2