IDT74FCT88915TT70PY IDT, Integrated Device Technology Inc, IDT74FCT88915TT70PY Datasheet - Page 8

• Manufacturer Part Number: IDT74FCT88915TT70PY
• Description: IC PLL CLK GENERATOR 28-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 74FCTr
• Type: Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of IDT74FCT88915TT70PY

• Pll: Yes with Bypass
• Input: LVTTL
• Output: LVCMOS, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/No
• Frequency - Max: 70MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: *
• Frequency-max: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 74FCT88915TT70PY

Q2, Q3 and Q4).
1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
internal PLL will line up the positive edges of Q/2 and SYNC. Thus the Q/2
frequency will equal the SYNC frequency. The Q outputs (Q0-Q4, Q5) will
always run at 2X the Q/2 frequency, and the 2Q output will run at 4X the Q/2
frequency.
1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
internal PLL will line up the positive edges of Q4 and SYNC. Thus the Q4
frequency (and the rest of the "Q" outputs) will equal the SYNC frequency. The
Q/2 output will always run at 1/2 the Q frequency, and the 2Q output will run
at 2X the Q frequency.
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
Allowable Input Frequency Range:
10MHz to (f2Q F
5MHz to (f2Q F
The frequency relationship shown here is applicable to all Q outputs (Q0, Q1,
In this application, the Q/2 output is connected to the FEEDBACK input. The
In this application, the Q4 output is connected to the FEEDBACK input. The
Figure 4a. Wiring Diagram and Frequency Relationships
12.5 M Hz
input
LO W
MAX
MAX
FEED BACK
REF_SEL
SYNC(0)
V
LF
GND(AN)
FQ_SEL
Spec)/8 (for FREQ_SEL LOW)
with Q/2 Output Feedback
CC
HIGH
Spec)/4 (for FREQ_SEL HIGH)
HIG H
RST
12.5 M Hz feedback signal
(AN)
Q 5
Q0
FCT88915TT
Q1
Q4
PLL_EN
HIGH
2Q
50 MHz signal
Q/2
Q3
Q 2
25 MHz
Outputs
Clock
"Q"
8
2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
internal PLL will line up the positive edges of 2Q and SYNC. Thus the 2Q
frequency will equal the SYNC frequency. The Q/2 output will always run at
1/4 the 2Q frequency, and the Q output will run at 1/2 the 2Q frequency.
Allowable Input Frequency Range:
20MHz to (f2Q F
10MHz to (f2Q F
In this application, the 2Q output is connected to the FEEDBACK input. The
Allowable Input Frequency Range:
40MHz to (f2Q F
20MHz to (f2Q F
50 MHz
input
25 MHz
input
LOW
Figure 4b. Wiring Diagram and Frequency Relationships
Figure 4c. Wiring Diagram and Frequency Relationships
LOW
25 MHz feedback signal
FEED BAC K
REF_SEL
SYN C(0)
V
LF
GN D(AN)
FQ_SEL
50 MH z feedback signal
FEEDBACK
REF_SEL
SYNC(0)
V
LF
GND(AN
)
FQ_SEL
CC
HIGH
HIGH
RST
RST
CC
HIGH
HIGH
(AN)
MAX
MAX
MAX
MAX
(AN)
with Q4 Output Feedback
with 2Q Output Feedback
Spec)/4 (for FREQ_SEL LOW)
Spec)/2 (for FREQ_SEL HIGH)
Spec)/2 (for FREQ_SEL LOW)
Spec) (for FREQ_SEL HIGH)
Q5
Q0
Q0
Q5
FCT88915TT
FCT88915T
T
COMMERCIAL TEMPERATURE RANGE
Q1
Q4
Q1
Q4
PLL_EN
PLL_EN
HIGH
2Q
HIGH
2Q
50 MHz signal
Q/2
Q3
Q2
Q/2
Q3
Q2
12.5 MHz
input
12.5 MHz
signal
25 MHz
Outputs
25 MH z
Outputs
Clock
Clock
"Q"
"Q"