ICS1523M IDT, Integrated Device Technology Inc, ICS1523M Datasheet - Page 10

• Manufacturer Part Number: ICS1523M
• Description: IC VIDEO CLK SYNTHESIZER 24-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock/Frequency Synthesizer (IF), Fanout Distribution, Frequency Generatorr

Specifications of ICS1523M

• Pll: Yes
• Input: Clock
• Output: LVPECL, SSTL-3
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/Yes
• Frequency - Max: 250MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Frequency-max: 250MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 1523M

MDS ICS1523 ZC
Section 9 Output Termination
9.1 PECL Description
The ICS1523 PECL outputs consist of open-drain,
current-source, pull-down transistors. An external
resistor network permits complete flexibility of logic
levels and source impedance. This section describes
the design procedure to select the resistor values and
the pull-down current for these devices.
9.2 PECL Output Structure
The output stage and external circuitry are shown
below in
pull-downs. The two output transistors switch
differentially, steering the current source
(programmable via RSET) from one output to the other.
Figure 9-1 PECL Termination Network
ICS1523
Figure
or CLK/2+ (Pin 23)
or CLK/2– (Pin 22)
9-1. The output devices are open-drain
CLK+ (Pin 21)
CLK– (Pin 20)
IREF (Pin 24)
Integrated Device Technology, Inc.
* Coaxial cable, microstrip, or stripline, with Z
coaxial cable, microstrip, or stripline is not required if the distance
from the ICS1523 to the PECL load is short (that is, < 3 cm).
V
DD
0.1μF
RSET

10
*
*
Tech Support: www.idt.com/go/clockhelp
Video Clock Synthesizer with I
For the high logic level, the output transistor is off, so
the logic level is set by the ratio of R
voltage VAA. Generally, VAA will be equal to VDD.
For logic low, the pull-down transistor turns on, pulling
the output voltage down to the low logic level.
Decoupling capacitor C1 should be a 0.01µF
high-frequency ceramic unit, and all power pins on the
ICS1523 should also be decoupled with similar
capacitors.
9.3 PECL Design Assumptions
All referenced voltages in this application note are
positive and referenced to the GND pin of the chip.
However, negative logic levels can be generated by
level shifting, i.e. connecting the VDD pin of the device
to system ground and the GND pin to a negative
voltage.
All logic levels must be between GND and the lesser of
VAA and VDD. Then, nodal equations are written, with
resistances transformed into conductances.
I
I
PECL
PECL
V
CC
R
R
A
B
0.1μF
R
R
2
0
C Programmable Delay
B
A
= R
L
. Typically,
A
Destination
and R
Revision 020811
Device
C
1
B
ICS1523
and the