ICS1523M IDT, Integrated Device Technology Inc, ICS1523M Datasheet - Page 8

• Manufacturer Part Number: ICS1523M
• Description: IC VIDEO CLK SYNTHESIZER 24-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock/Frequency Synthesizer (IF), Fanout Distribution, Frequency Generatorr

Specifications of ICS1523M

• Pll: Yes
• Input: Clock
• Output: LVPECL, SSTL-3
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/Yes
• Frequency - Max: 250MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Frequency-max: 250MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 1523M

MDS ICS1523 ZC
Section 5 Register Set Details
Register Conventions
Note 3- COAST - Charge Pump Enable/Disable
The COAST input can be used to disable the charge
pump during the vertical blanking interval if the input
HSYNC input changes frequency during this time. The
charge pump is asynchronously disabled and
synchronously re-enabled on the second input HSYNC
after the disable signal goes invalid. This pin can be
connected to VSYNC or pulled to either rail if unused.
Note 4 - LOCK/REF Function
Note 5- CLK Output Divider
SSTL_3 CLK Freq. = Output Freq. / CLK Divider
EnPLS
CP_Pol
0xY:Z = Register Index Y(hex), bit Z
0xY:Z~Q = Register Index Y(hex), bit Z to Q
bit 7~6
0x6 bit 7,6
0x0:1~0
0x0
0 0
0 1
1 0
1 1
1 1
0 0
x 1
1 0
0 0
0 1
1 0
1 1
-
CPen
0x7bit 7 LOCK/REF Output
IN_SEL
Integrated Device Technology, Inc.
0
1
-
-
-
Charge Pump Enabled If...
COAST (Pin 5) = 1
Always Enabled (Default)
COAST (Pin 5) = 0
1 (default)
CLK Divider
2
4
8
PLL locked = 1 else 0
RESERVED
Post Schmitt trigger
0
HSYNC (pin 7) XOR
REF_Pol (0x0:2)
F
OSC
/ (OSC _DIV +2)

8
Tech Support: www.idt.com/go/clockhelp
Video Clock Synthesizer with I
Note 6 - ICP - Charge Pump Current
Increasing the charge pump current makes the loop
respond faster, raising the loop bandwidth. The typical
value when using the internal loop filter is 011.
Note 7 - VCO Divider
This is used to keep the VCO running at faster speeds
even when the output frequency is low.
VCO speed = Output Frequency * VCO Scaler
Note 8 - DPA Offset Ranges
Using the DPA above 160 MHz is not recommended.
Set DPA_OS = 0 for speeds in excess of 160 MHz to
bypass the DPA.
bit 1-0
0x5
Bit 2~0
0 0
0 1
1 0
1 1
0x1:bit 5,4
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0x1
0 0
0 1
1 0
1 1
# of DPA Delay
Elements (d)
Charge Pump Current (μA)
8 (Typical Internal Filter Value)
16
32
64
VCO Divider
2 (default)
4
8
16
Reserved
Reserved
Max. (h)
bit 5-0
2
0x4
C Programmable Delay
0F
1F
3F
16
32
64
1
2
4
Clock Range (MHz)
Min
Revision 020811
48
24
12
ICS1523
Max
160
80
40