ICS1523M IDT, Integrated Device Technology Inc, ICS1523M Datasheet
ICS1523M
Specifications of ICS1523M
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ICS1523M Summary of contents
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Video Clock Synthesizer with I General Description The ICS1523 is a low-cost, high-performance frequency generator well suited to general purpose phase controlled clock synthesis as well as line-locked and genlocked high-resolution video applications. Using IDT’s advanced low-voltage CMOS ...
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Section 1 Operational Description 1.1 Naming Conventions 0xY = Register Index Y(hex) 0xY:Z = Register Index Y(hex), bit Z 0xY:Z~Q = Register Index Y(hex), bit 1.2 Overview The ICS1523 is a general purpose, high-performance, I2C programmable clock ...
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MHz even if a low output frequency is required.The output of the VCOD is the full speed output frequency seen on the CLK pins. 1.7 Dynamic Phase Adjust (DPA) The VCOD output clock is then sent through the DPA for ...
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Section 2 Pin Descriptions PIN PIN NAME TYPE NO. 1 VDDD POWER 2 VSSD POWER 3 SDA IN/OUT 4 SCL IN 5 COAST IN 6 EXTFB IN 7 HSYNC IN 8 EXTFIL IN 9 XFILRET IN 10 VDDA POWER 11 ...
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Section 3 Functional Block Diagram MDS ICS1523 ZC Integrated Device Technology, Inc. Video Clock Synthesizer with I 5 Tech Support: www.idt.com/go/clockhelp ICS1523 2 C Programmable Delay Revision 020811 ...
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Section 4 Register Set Summary Reg. Index Name Access Bit Name 0x0 Input CPen Control CP_Pol Ref_Pol Fbk_Pol Fbk_Sel Func_Sel EnPLS EnRef 0x1 Loop ICP0-2 Control Reserved VCOD0-1 Reserved 0x2 FdBk Div 0 R ...
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Register Set Summary (continued) Reg. Name Access Bit Name Index 0x6 Output OE_Pck Enables OE_Tck OE_P2 OE_T2 OE_F Ck2_Inv Out_Scl 0x7 Osc_Div Osc_Div 0-6 In-Sel 0x8 Reset Write DPA PLL 0x10 Chip Ver ...
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Section 5 Register Set Details Register Conventions 0xY:Z = Register Index Y(hex), bit Z 0xY:Z~Q = Register Index Y(hex), bit Note 3- COAST - Charge Pump Enable/Disable CP_Pol CPen 0x0:1~0 Charge Pump Enabled If... 0 0 COAST ...
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The DPA Resolution Select register (0x5:0~1) is double-buffered. Working registers are loaded only after a DPA software reset (0x8=xA) For more details, See Figure 11.2 Section 6 OSC Divider and REF The ICS1523 accepts a single-ended clock on pin 12, ...
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Section 9 Output Termination 9.1 PECL Description The ICS1523 PECL outputs consist of open-drain, current-source, pull-down transistors. An external resistor network permits complete flexibility of logic levels and source impedance. This section describes the design procedure to select the resistor ...
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PECL Example Determine V and V for target device, as follows OL OH (see also Figure 9-1): 1. Choose (VCC * VOH RA) / ...
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Section 11 Programming 2 11.1 Industry-Standard I C Serial Bus: Data Format Figure 11-1 ICS1523 Data Format for I Write Procedure for Single Re gis ter MSB LSB Device address ...
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Programming Flow for Modifying PLL and DPA Settings (Coast disabled, Positive edge of HSYNC, Internal Feedback, FUNC = regenerated HSYNC, PLL lock status to LOCK (STATUS) pin Decrement Charge Pump Current Reg0x1:2~0 MDS ICS1523 ZC Integrated Device Technology, Inc. ...
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Section 12 Timing Diagrams Figure 12-1 DPA Operation HSYNC DPA Offset when DPA_OS [5- DPA Offset when DPA_OS [5- DPA Offset when DPA_OS [5- DPA Offset when DPA_OS [5-0] = Max ...
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Timing for 0x0:2=0 Figure 12-2 0x0:2=0 Timing Diagram 0x0:2=0 Timing Values Table 12-2 Symbol Parameter T2 HSYNC High to FUNC High (DPA Offset = 0) T3 HSYNC High to PECL CLK+ High (DPA Offset = 0) T4 PECL Clock ...
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Timing for 0x0:2=1 Figure 12-3 0x0:2=1 Timing Diagram 0x0:2=1 Timing Values Table 12-3 Symbol Parameter T2 HSYNC Low to FUNC High Delay T3 HSYNC Low to PECL CLK+ High Delay (DPA Offset = 0) T4 PECL Clock to SSTL_3 ...
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HSYNC to REF Timing Figure 12-4 HSYNC to REF Timing Diagram Reg0 Reg0 Table 12-4 HSYNC to REF Timing Diagram Symbol Parameter T HSYNC Low to REF Delay 0 T HSYNC High to REF Delay ...
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Section 13 AC/DC Operating Conditions 13.1 Absolute Maximum Ratings Table 13-1 lists absolute maximum ratings for the ICS1523. Stresses above these ratings can cause permanent damage to the device. These ratings, which are standard values for ICS commercially rated parts, ...
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Parameter Analog Input (HSYNC) Input High Voltage Input Low Voltage Digital Inputs (SDA, SCL, EXTFB, OSC, I Input High Voltage Input Low Voltage Input Hysteresis POR Threshold SDA Digital Output SDA Output Low Voltage SDA Output High Voltage PECL Outputs ...
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Table 13-5 Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case MDS ICS1523 ZC Integrated Device Technology, Inc. Video Clock Synthesizer with I Symbol Conditions Min. θ Still Air JA θ 1 m/s air flow JA ...
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... Part / Order Number 1523MLF ICS1523MLF 1523MLFT ICS1523MLF Note: “LF” denotes Pb (lead) free package. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use ...