LMX2470SLEX National Semiconductor, LMX2470SLEX Datasheet - Page 22

• Manufacturer Part Number: LMX2470SLEX
• Description: IC PLL DELTA-SIGMA 24LAMUCSP
• Manufacturer: National Semiconductor
• Type: PLL Frequency Synthesizer, Delta Sigmar

Specifications of LMX2470SLEX

• Pll: Yes with Bypass
• Input: CMOS
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:3
• Differential - Input:output: Yes/No
• Frequency - Max: 2.6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-Laminate UTCSP
• Frequency-max: 2.6GHz
• For Use With: LMX2470EVAL - EVALUATION BOARD FOR LMX2470
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LMX2470SLEX; *LMX2470SLEX/NOPB; LMX2470SLEXCT

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Functional Description
1.6.4 RF PLL Fastlock Reference Table and Example
The table below shows most of the trade-offs involved in
choosing a steady-state charge pump current (RF_CPG),
The above table shows various combinations for using
RF_CPG, RF_CPF, and CSR. Although this table does not
show all possible combinations, it does show all the modes
that give the best possible performance. To use this table,
choose a CSR factor on the horizontal axis, then a fastlock
loop bandwidth multiplier on the vertical axis, and the table
will show all possible combinations of steady state current,
Fastlock current, and what resistor value (R2’) to use during
Fastlock. In order to better illustrate the cycle slipping and
Fastlock circuitry, consider the following example:
The comparison frequency is 20 MHz and the loop band-
width is 10 KHz. 20 MHz is a good comparison freqeuncy to
use because it yields the best phase noise performance.
This ratio of the comparison frequency to the loop bandwidth
is 2000, so cycle slipping will occur and degrade the lock
time, unless something is done to prevent it. Because the
filter is fourth order, it would be difficult to keep the loop filter
optimized if the loop gain multiplier, K was not one. For this
reason, choosing a loop gain multiplier of one makes sense.
One solution is to set the steady state current to be 100 µA,
and the fastlock current to be 1600 µA. The CSR factor could
be set to 1/16 and reduce this ratio to 2000/16 = 125.
However, using 100 µA charge pump current has phase
noise that is significantly worse than the higher charge pump
current modes. A better solution would be to use 200 µA
Comparison Frequency 10 MHz x 2 = 20 MHz (OSC2X = 1)
PLL Loop Bandwidth
Parameter
Output Frequency
Crystal Reference
Loop Filter Order
RF_CPG
RF_CPF
CSR
1. Allows capacitors in loop filter to be smaller
values making it easier to find physically smaller
components and components with better dielectric
properties.
2. Allows a larger loop bandwidth multiplier for
fastlock, or a higher cycle slip reduction factor.
The only reason not to always choose this to 1600
µA is to make it such that no resistor is required for
fastlock. For 3rd and 4th order filters, it is not
possible to keep the filter perfectly optimized by
simply switching in a resistor for fastlock.
Do not choose this any larger than necessary to
eliminate cycle slipping. Keeping this small allows a
larger loop bandwidth multiplier for fastlock.
Advantages to Choosing Smaller
4th ( i.e. 7 components )
1930 – 1990 MHz
(Continued)
10 MHz
10 KHz
22
the Fastlock charge pump current (RF_CPF), and the Cycle
Slip Reduction Factor (CSR).
current and 1600 µA X2 ( using PDCP = X2 Fastlock ), since
the 200 µA mode will have better phase noise. Depending on
how important phase noise is, it could make sense to use a
higher steady state current. Using 800 µA steady state cur-
rent provides much better phase noise than 200 uA ( about 5
dB ), but then the cycle slip reduction factor would need to be
reduced to 4. In general, it is good practice to use the PDCP
= X2 fastlock mode whenever cycle slip reduction is used, so
that the best phase noise can be achieved. If the
factor is used, then the ratio of comparison frequency to loop
bandwidth in fastlock is reduced to 250. There may be some
cycle slipping, but the phase noise benefit of using the higher
charge pump current may be worth it. If phase noise is even
more important, it might even make sense to have a steady
state current of 1600 µA and use a CSR factor of
PDCP mode of X2 Fastlock. Another consideration is that
the comparison frequency could be lowered in the steady
state mode to reduce cycle slipping. This sacrifices phase
noise for lock time. In general, using Fastlock and CSR is not
the same for every application. There is a trade-off of lock
time vs. phase noise. It might be tempting to try to achieve
the best Fastlock benefit by using a K value of 32. Even if the
loop filter could be kept well optimized in Fastlock, this
hypothetical design would probably switch very fast when
the Fastlock was engaged, but then when Fastlock is disen-
gaged, a large frequency glitch would appear, and the ma-
jority of the lock time would consist of waiting for this glitch to
settle out. Although this would definitely improve the lock
time, even accounting for the glitch, the same result could
probably be obtained by using a lower K value, like 8, and
having better phase noise instead.
Phase noise, especially within the loop bandwidth of
the system
will be slightly worse for lower charge pump
currents.
This allows the maximum possible benefit for
fastlock.
This will eliminate cycle slips better.
Advantages to Choosing Larger
1
⁄
2
1
and the
⁄
4
CSR