SI5325B-C-GM Silicon Laboratories Inc, SI5325B-C-GM Datasheet - Page 42

• Manufacturer Part Number: SI5325B-C-GM
• Description: IC UP-PROG CLK MULTIPLIER 36-QFN
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5325B-C-GM

• Number Of Circuits: 1
• Package / Case: 36-QFN
• Pll: Yes
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 808MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 1.71 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 808MHz
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 10 MHz
• Output Frequency Range: 10 MHz to 808 MHz
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 1.71 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5325
Reset value = 0000 0000
42
Register 136.
Name RST_REG
Type
Bit
5:2
1:0
Bit
7
6
GRADE_RO
RST_REG
Reserved
R/W
Name
D7
ICAL
[1:0]
Internal Reset (Same as Pin Reset).
Note: The I2C (or SPI) port may not be accessed until 10 ms after RST_REG is asserted.
0: Normal operation.
1: Reset of all internal logic. Outputs disabled or tristated during reset.
Start an Internal Calibration Sequence.
For proper operation, the device must go through an internal calibration sequence. ICAL
is a self-clearing bit. Writing a one to this location initiates an ICAL. The calibration is
complete once the LOL alarm goes low. A valid stable clock (within 100 ppm) must be
present to begin ICAL.
Note: Any divider, CLKINn_RATE or BWSEL_REG changes require an ICAL to take
effect.
0: Normal operation.
1: Writing a "1" initiates internal self-calibration. Upon completion of internal self-calibra-
tion, LOL will go low.
Reserved.
Indicates Maximum Clock Output Frequency of this Device.
Limits the range of the N1_HS divider.
00: N1_HS x NCn_LS > 4. Maximum clock output frequency = 1.4175 GHz.
01: N1_HS x NCn_LS > 6. Maximum clock output frequency = 808 MHz.
10: N1_HS x NCn_LS > 14. Maximum clock output frequency = 346 MHz.
11: N1_HS x NCn_LS > 20. Maximum clock output frequency = 243 MHz.
ICAL
R/W
D6
D5
Preliminary Rev. 0.4
D4
Reserved
R
Function
D3
D2
GRADE_RO [1:0]
D1
R
D0