PI6C39911-2JE Pericom Semiconductor, PI6C39911-2JE Datasheet - Page 2

• Manufacturer Part Number: PI6C39911-2JE
• Description: IC PROG SKEW CLOCK DRIVER 32PLCC
• Manufacturer: Pericom Semiconductor
• Series: SuperClock®r
• Type: Clock Bufferr

Specifications of PI6C39911-2JE

• Pll: Yes
• Input: LVTTL
• Output: LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 1:8
• Differential - Input:output: No/No
• Frequency - Max: 133MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.97 V ~ 3.63 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes:
1. For all three-state inputs, HIGH indicates a connection to V
2. The level to be set on FS is determined by the “normal” operating frequency (f
Pin Descriptions
4
F
1
2
3
H
L
connection. Internal termination circuitry holds an unconnected input to V
Nominal frequency (f
2). The frequency appearing at the REF and FB inputs will be f
of the REF and FB inputs will be f
as the FB input.
2
3
4
1
M
S
Q
Q
Q
Q
O
G I
S
F
F
F
N
F
V
T
V
Table 1. Frequency Range Select and t
G
(
D I
R
, 1
, 0
, 0
g i
, 0
, 0
, 0
, 0
, 0
, 0
W
F
F
E
a
C
C
H
N
E
) 2
m
B
S
S
n
C
C
08-0298
F
2
3
4
2
3
4
1
1
D
l a
T
N
Q
e
F
F
F
Q
Q
Q
F
Q
1
1
1
1
1
1
1
1
M
2 1
F
0 4
5 2
N
P
P
P
. n i
5 .
I
O
W
W
W
O
O
O
O
O /
I
I
I
I
I
I
I
I
M
R
R
R
(
M
O
O
O
O
r G
R
P
T
T
T
T
T
T
P
P
M
H
NOM
1
L
r h
r h
r h
r h
r h
r h
o
o
0 3
0 5
e
t u
t u
t u
t u
3 3
) z
a
u o
r e f
w
w
L
e e
e e
e e
e e
e e
e e
. x
u p
u p
u p
u p
r e
r e
d n
e f
n e
l -
e l -
e l -
e l -
e l -
l -
) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table
p t
p t
p t
p t
d e
v e
v e
u s
u s
e c
e v
e v
e v
e v
t
r i a
r i a
r i a
r i a
a b
p p
p p
U
l e
l e
f l
f l
f l
f l
r f
=
w
k c
e r f
e s
1
2
3
4
y l
y l
q e
NOM
n u
n u
n u
n u
e h
s .
s .
s .
s .
f
e l
f
f
u q
NOM
e u
n i
i t c
i t c
i t c
i t c
r o
r o
e r
4 4
6 2
6 1
. t c
e e
e e
e e
e e
u p
c n
n e
n o
n o
n o
n o
/2 or f
o
n i
1
N
S
T
T
T
T
( t
i y
y c
t u
r e t
× N
=
b a
b a
b a
b a
s
s
s
s
e e
u p
y t
l e
l e
l e
l e
U
p n
r
a n
e l
e l
e l
e l
c e
c e
c e
c e
NOM
i p
n a
Calculation
e t
d t
t u
c l
a c
2
2
2
2
i t
i t
i t
i t
t s
e g
w
i r
F
u s
c r i
y l l
p n
p n
p n
p n
i h
m
e v
A
e r
/4 when the part is configured for a frequency multiplication by using a divided output
e s
p p
h c
o
t i u
p
t u
t u
t u
t u
s r
q
c
p
e l
e d
( .
n o
e i l
f s
f s
f s
f s
y r
o r
2 2
8 3
2 6
t c
t
U
M
t s
e n
r o
r o
r o
r o
i x
e s
s .
7 .
5 .
5 .
=
H
m
e h
t c
i t c
(1)
e e
o
o
o
o
1
) z
a
d e
0 .
t u
t u
t u
t u
n o
e t
e r f
t a
T
s n
u p
u p
u p
u p
b a
o t
CC
u q
n u
p t
p t
p t
p t
e l
o
e d
, LOW indicates a connection to GND, and MID indicates an open
2
n e
NOM
e n
r i a
r i a
r i a
r i a
. 1
y c
t r
o
1
2
3
4
1
e h
3
t f
a
F
F
H
H
H
when the output connected to FB is undivided. The frequency
L
L
L
D
1 (
2 (
3 (
4 (
Programmable Skew Clock Buffer - SuperClock
d n
M
M
M
, 1
, 1
e h
O
O
O
G I
G I
G I
b
e
Q
Q
Q
Q
F
D I
D I
D I
o l
2
W
W
W
4
c s
i t
u
H
H
H
, 0
, 0
, 0
, 0
Table 2. Programmable Skew Configurations
i e
F
k c
F
NOM
i m
n
, 1
3.3V High Speed LVTTL or Balanced Output
i r
1
h g
t c
CC
g n
1
2
3
4
t p
i d
o i
o t
Q
Q
Q
Q
/2.
) and Time Unit Generator (see Logic Block Diagram).
o i
g a
n
a
) 1
) 1
) 1
) 1
t u
a g
n
S
a r
s .
s .
s .
s .
1
3
u p
l e
n i
F
m
F
L
H
L
H
L
H
c e
e e
e e
e e
e e
M
M
M
, 0
t s
) s t
, 0
O
O
O
G I
G I
G I
e d
s t
D I
D I
D I
2
W
W
W
w
4
T
T
T
T
H
H
H
F
c s
F
b a
b a
b a
b a
i h
, 0
0
h c
p i r
e l
e l
e l
e l
o i t
l l a
. 2
. 2
. 2
. 2
s n
1
u f
2
Q
Q
c n
+
+
+
+
, 0
–
–
–
–
, 0
t 0
t 4
t 3
t 2
t 1
o i t
t 1
t 2
t 3
t 4
1
U
2
U
U
U
U
U
U
U
U
a n
Q
Q
, 1
1
v l
O
u
i r a
p t
D
D
3
i t a
t u
i v i
i v i
Q
n o
+
+
+
–
–
–
, 0
e d
e d
F
t 0
t 6
t 4
t 2
t 2
t 4
t 6
u
U
3
n
U
U
U
U
U
U
s i
y b
y b
Q
PS8497I
t c
m
1
o i
2
4
PI6C39911
a e
s n
D
u s
4
(1)
I
Q
i v i
e r
v n
–
–
–
+
+
+
, 0
e d
t 0
. d
t r e
t 6
t 4
t 2
t 2
t 4
t 6
U
11/06/08
4
U
U
U
U
U
U
y b
d e
Q
1
2
® ® ® ® ®