CY28339ZXC Cypress Semiconductor Corp, CY28339ZXC Datasheet - Page 11

• Manufacturer Part Number: CY28339ZXC
• Description: IC CLOCK SYNTHESIZER 48-TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Spread Spectrum Clock Generatorr

Specifications of CY28339ZXC

• Pll: Yes
• Input: LVTTL, Crystal
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 8:16
• Differential - Input:output: No/No
• Frequency - Max: 133MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP II
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-07507 Rev. *A
Table 4. CPU Clock Current Select Function
Table 5. Group Timing Relationship and Tolerances
USB_48M and DOT_48M Phase Relationship
The USB_48M and DOT_48M clocks are in phase. It is under-
stood that the difference in edge rate will introduce some
inherent offset. When 3V66_1/VCH clock is configured for
VCH (48-MHz) operation it is also in phase with the USB and
DOT outputs. See Figure 11 .
66IN to 66BUFF(0:2) Buffered Prop Delay
The 66IN to 66BUFF(0:2) output delay is shown in
Figure 12 .The Tpd is the prop delay from the input pin (66IN)
to the output pins (66BUFF[0:2]). The outputs’ variation of Tpd
is described in the AC parameters section of this data sheet.
The measurement taken at 1.5V.
3V66 to PCI
USB_48M to DOT_48M Skew
66BUFF(0:2) to PCI offset
Board Target Trace/Term Z
66IN
66B
PCIF
66B
PCI
USB_48M
DOT_48M
Description
50 Ω
50 Ω
Tpd
3.5ns
Figure 13. Buffer Mode – 33V66_0; 66BUFF(0:2) Phase Relationship
1.5-
Figure 11. USB_48M and DOT_48M Phase Relationship
Figure 12. 66IN to 66BUFF(0:2) Output Delay Figure
Reference R, Iref – Vdd (3*Rr)
Offset
2.5 ns
0.0 ns
2.5 ns
Rr = 330 1%, Iref = 3.33mA
Rr = 475 1%, Iref = 2.32mA
Tolerance
66BUFF(0:2) to PCI Buffered Clock Skew
Figure 13 shows the difference (skew) between the 3V33(0:5)
outputs when the 66M clocks are connected to 66IN. This
offset is described in the Group Timing Relationship and Toler-
ances section of this data sheet. The measurements were
taken at 1.5V.
3V66 to PCI Un-Buffered Clock Skew
Figure 1 shows the timing relationship between 3V66_0 and
PCI(0:2,4:8) and PCIF when configured to run in the unbuf-
fered mode.
± 1.0 ns
± 1.0 ns
± 1.0 ns
3V66 leads PCI (unbuffered mode)
0 degrees phase shift
66BUFF leads PCI (buffered mode)
Output Current
Ioh = 6*Iref
Ioh = 6*Iref
Conditions
CY28339
1.0V @ 50
0.7V @ 50
Page 11 of 18
Voh @ Z
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