CY28339ZXC Cypress Semiconductor Corp, CY28339ZXC Datasheet - Page 15

• Manufacturer Part Number: CY28339ZXC
• Description: IC CLOCK SYNTHESIZER 48-TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Spread Spectrum Clock Generatorr

Specifications of CY28339ZXC

• Pll: Yes
• Input: LVTTL, Crystal
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 8:16
• Differential - Input:output: No/No
• Frequency - Max: 133MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP II
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-07507 Rev. *A
AC Electrical Specifications
Test and Measurement Set-up
For Differential CPU Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Parameter
CCJ
DC
PERIOD
R
CCJ
DC
PERIOD
R
CCJ
DC
PERIOD
R
CCJ
PZL
PZL
STABLE
SS
SH
SU
/ T
/ T
/ T
/T
/T
F
F
F
PZH
PZH
PCIF and PCI Cycle to
Cycle Jitter
USB_48M Duty Cycle
USB_48M Period
USB_48M Rise and Fall Times
REF Duty Cycle
REF Period
REF Rise and Fall Times
REF Cycle to Cycle Jitter
Output Enable Delay (All Outputs)
Output Disable Delay (All Outputs)
Clock Stabilization from Power-up
Stopclock Set Up Time
Stopclock Hold Time
Oscillator Start-up time
DOT_48M Duty Cycle
DOT_48M Period
DOT_48M Rise and Fall Times
DOT_48M Cycle to Cycle Jitter
DOT_48M Cycle to Cycle Jitter
C P U C
C P U T
Description
3 30Ω
(continued)
Figure 15. 1.0V Test Load Termination
ENABLE/DISABLE and SETUP
T
T
P C B
P C B
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measured between 0.4V and 2.4V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measured between 0.4V and 2.4V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measured between 0.4V and 2.4V
Measurement at 1.5V
When XIN is driven from external clock source
CPU_STOP# and PIC_STOP# set up time with
respect to PCIF clock to guarantee that the
effected clock will stop or start at the next PCIF
clock’s rising edge.
When crystal meets min. 40 Ω device series resis-
tance specification
DOT_48M
USB_48M
63.4 Ω
REF
Condition
475Ω
63 .4Ω
33.2Ω
33.2Ω
2pF
2p F
M easurem ent P oint
M easurem ent P oint
69.827 69.855
20.83
20.82
Min.
10.0
0.5
1.0
1.0
1.0
1.0
45
45
45
–
–
–
–
–
0
CY28339
20.83
20.83
Max.
1000
10.0
10.0
Page 15 of 18
250
350
350
1.0
2.0
4.0
3.0
55
55
55
–
–
V/ns
Unit
ms
ps
ns
ns
ps
ns
ns
ps
ns
ps
ns
ns
ns
ns
%
%
%
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