CY28339ZXC Cypress Semiconductor Corp, CY28339ZXC Datasheet
CY28339ZXC
Specifications of CY28339ZXC
Available stocks
Related parts for CY28339ZXC
CY28339ZXC Summary of contents
Page 1
... TCLK is a test clock driven on the XTAL_IN input during test mode driven to a level between 1.0V and 1.8V. If the S2 pin level during power-up state will be latched into the device’s internal state register. Cypress Semiconductor Corporation Document #: 38-07507 Rev. *A Intel CK408 Mobile Clock Synthesizer • ...
Page 2
Pin Definitions Pin Number Name 47 REF0 1 XIN 2 XOUT 43, 42, CPUT1,CPUC1 39, 38 CPUT2, CPUC2 29 3V66_0 31 3V66_1/VCH 20 66IN/3V66_5 17, 18, 19 66BUFF [2:0] /3V66 [4:2] 6 PCIF 8, 9, 10, 12, 13, PCI [0:2] ...
Page 3
Two-Wire SMBus Control Interface The two-wire control interface implements a Read/Write slave only interface according to SMBus specification. The device will accept data written to the D2 address and data may read back from address D3. It will not respond ...
Page 4
Byte 2:PCI Clock Control Register (all bits are Read and Write functional) Bi @Pu Nam REF REF Output Control high strength low strength PCI6 PCI6 Output Control ...
Page 5
Byte 6: Silicon Signature Register (all bits are Read-only) Bit @Pup Name Byte 7: Reserved Register Bit @Pup Name ...
Page 6
Dial-a-Frequency Features SMBus Dial-a-Frequency feature is available in this device via Byte8 and Byte9 large-value PLL constant that depends on the frequency selection achieved through the hardware selectors (S1, S0). P value may be determined from Table ...
Page 7
PWRDWN# CPUT 133MHz CPUC 133MHz PCI 33MHz 3V66 USB 48MHz REF 14.318MHz Figure 2. Power-down Assertion Timing Waveforms – Unbuffered Mode ...
Page 8
PD# Deassertion The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 3.0 ms. 66Buff1 / GMCH 66Buff PCIF / APIC 33MHz PCI 33M Hz PW RDW N# CPU ...
Page 9
CPU_STOP# Deassertion The deassertion of the CPU_STOP# signal will cause all CPUT/C outputs that were stopped to resume normal operation in a synchronous manner (meaning that no short or stretched clock pulses will be produces when the clock resumes). The ...
Page 10
PCI_STP# PCIF PCI Figure 8. PCI_STOP# Deassertion Waveform VID (0:3), SEL (0,1) VTT_PWRGD# PWRGD 0.2-0.3mS VDD Clock Gen Delay Clock State State 0 State 1 Off Clock Outputs Off Clock VCO VDDA = 2.0V S0 Power Off Figure 10. Clock ...
Page 11
Table 4. CPU Clock Current Select Function Board Target Trace/Term Z 50 Ω 50 Ω Table 5. Group Timing Relationship and Tolerances Description 3V66 to PCI USB_48M to DOT_48M Skew 66BUFF(0:2) to PCI offset USB_48M and DOT_48M Phase Relationship The ...
Page 12
Buffer Characteristics Current Mode CPU Clock Buffer Characteristics The current mode output buffer detail and current reference circuit details are contained in the previous table of this data sheet. The following parameters are used to specify output buffer characteristics: VDD3 ...
Page 13
Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J ESD ESD Protection (Human Body Model) HBM Ø ...
Page 14
AC Electrical Specifications (continued) Parameter Description CPUT and CPUC Rise and Fall R F Times T Rise/Fall Matching RFM ∆ T Rise Time Variation R ∆ T Fall Time Variation F V Crossing Point Voltage at 0.7V ...
Page 15
AC Electrical Specifications (continued) Parameter Description T PCIF and PCI Cycle to CCJ Cycle Jitter T DOT_48M Duty Cycle DC T DOT_48M Period PERIOD DOT_48M Rise and Fall Times DOT_48M Cycle to Cycle Jitter ...
Page 16
... CPUT 33Ω CPUC 475Ω 2.4V 1.5V 0.4V Tr Ordering Information Part Number CY28339ZC CY28339ZCT Lead Free CY28339ZXC CY28339ZCXT Document #: 38-07507 Rev PCB Measurement Point 49.9Ω 2pF T Measurement Point PCB 2pF 49.9Ω Figure 16. 0.7V Test Load Termination Output under Test 3 ...
Page 17
... Document #: 38-07507 Rev. *A © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...
Page 18
Document History Page Document Title: CY28339 Intel CK408 Mobile Clock Synthesizer Document Number: 38-07507 Issue Orig. of REV. ECN NO. Date Change ** 122362 12/13/02 *A 237868 See ECN Document #: 38-07507 Rev. *A Description of Change RGL New ...