MC145152DW2R2 Freescale Semiconductor, MC145152DW2R2 Datasheet - Page 21

• Manufacturer Part Number: MC145152DW2R2
• Description: IC PAR-IN PLL FREQ SYNTH 28-SOIC
• Manufacturer: Freescale Semiconductor
• Type: PLL Clock/Frequency Synthesizerr

Specifications of MC145152DW2R2

• Pll: Yes
• Input: Clock
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/No
• Frequency - Max: 25MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 9 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Frequency-max: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: MC145152DW2TR

To verify that the maximum dc supply voltage does not overdrive the crystal, monitor the output frequency
as a function of voltage at OSC
increase very slightly as the dc supply voltage is increased. An overdriven crystal will decrease in
frequency or become unstable with an increase in supply voltage. The operating supply voltage must be
reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the
oscillator start-up time is proportional to the value of R1.
Through the process of supplying crystals for use with CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals. Discussions with such manufacturers can
prove very helpful.
4.3
4.3.1
The technique of dual-modulus prescaling is well established as a method of achieving high performance
frequency synthesizer operation at high frequencies. Basically, the approach allows relatively
low-frequency programmable counters to be used as high-frequency programmable counters with speed
capability of several hundred MHz. This is possible without the sacrifice in system resolution and
performance that results if a fixed (single-modulus) divider is used for the prescaler.
In dual-modulus prescaling, the lower speed counters must be uniquely configured. Special control logic
is necessary to select the divide value P or P + 1 in the prescaler for the required amount of time (see
modulus control definition).
4.3.2
The system total divide value, N
N is the number programmed into the ÷ N counter, A is the number programmed into the ÷ A counter, P
and P + 1 are the two selectable divide ratios available in the dual-modulus prescalers. To have a range of
N
the ÷ N counter. N is then incremented to N + 1 and the ÷ A is sequenced from 0 through P - 1 again.
There are minimum and maximum values that can be achieved for N
and the size of the ÷ N and ÷ A counters.
The constraint N ≥ A always applies. If A
(P - 1) P since A is free to assume the value of 0.
To maximize system frequency capability, the dual-modulus prescaler output must go from low to high
after each group of P or P + 1 input cycles. The prescaler should divide by P when its modulus control line
is high and by P + 1 when its MC is low.
Freescale Semiconductor
T
values in sequence, the ÷ A counter is programmed from zero through P - 1 for a particular value N in
Dual-Modulus Prescaling
Overview
Design Guidelines
MC145151-2 and MC145152-2 Technical Data, Rev. 5
out
total
N
. (Care should be taken to minimize loading.) The frequency should
T
=
(N
frequency into the phase detector
T
frequency into the prescaler
) will be dictated by the application:
max
N
Tmax
= P - 1, then N
= N
max
• P + A
min
≥ P - 1. Then N
max
= N
T
•
. These values are a function of P
P + A
Tmin
Design Considerations
= (P - 1) P + A or
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