MC145152DW2R2 Freescale Semiconductor, MC145152DW2R2 Datasheet - Page 4

• Manufacturer Part Number: MC145152DW2R2
• Description: IC PAR-IN PLL FREQ SYNTH 28-SOIC
• Manufacturer: Freescale Semiconductor
• Type: PLL Clock/Frequency Synthesizerr

Specifications of MC145152DW2R2

• Pll: Yes
• Input: Clock
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/No
• Frequency - Max: 25MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 9 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Frequency-max: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: MC145152DW2TR

MC145151-2 Parallel-Input (Interfaces with Single-Modulus Prescalers)
N0 - N11
N Counter Programming Inputs (Pins 11 - 20, 22 - 25)
These inputs provide the data that is preset into the ÷ N counter when it reaches the count of zero. N0 is
the least significant and N13 is the most significant. Pull-up resistors ensure that inputs left open remain
at a logic 1 and require only an SPST switch to alter data to the zero state.
T/R
Transmit/Receive Offset Adder Input (Pin 21)
This input controls the offset added to the data provided at the N inputs. This is normally used for offsetting
the VCO frequency by an amount equal to the IF frequency of the transceiver. This offset is fixed at 856
when T/R is low and gives no offset when T/R is high. A pull-up resistor ensures that no connection will
appear as a logic 1 causing no offset addition.
OSC
Reference Oscillator Input/Output (Pins 27, 26)
These pins form an on-chip reference oscillator when connected to terminals of an external parallel
resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSC
ground and OSC
signal. This signal is typically ac coupled to OSC
levels) dc coupling may also be used. In the external reference mode, no connection is required to OSC
1.2.2
PD
Phase Detector A Output (Pin 4)
Three-state output of phase detector for use as loop-error signal. Double-ended outputs are also available
for this purpose (see φ
Frequency f
Frequency f
Frequency f
φ
Phase Detector B Outputs (Pins 8, 9)
These phase detector outputs can be combined externally for a loop-error signal. A single-ended output is
also available for this purpose (see PD
If frequency f
pulsing low. φ
If the frequency f
pulsing low. φ
If the frequency of f
minimum time period when both pulse low in phase.
4
R
, φ
out
in
V
, OSC
Output Pins
V
V
V
V
out
> f
< f
= f
R
V
is greater than f
remains essentially high.
remains essentially high.
out
R
R
R
V
or f
or f
and Phase Coincidence: High-Impedance State
is less than f
to ground. OSC
V
= f
V
V
V
and φ
Leading: Negative Pulses
Lagging: Positive Pulses
R
and both are in phase, then both φ
MC145151-2 and MC145152-2 Technical Data, Rev. 5
R
).
R
R
or if the phase of f
or if the phase of f
in
may also serve as the input for an externally-generated reference
out
).
in
, but for larger amplitude signals (standard CMOS logic
V
V
is leading, then error information is provided by φ
is lagging, then error information is provided by φ
V
and φ
R
remain high except for a small
Freescale Semiconductor
in
to
out
V
R
.