LMX2332USLBX National Semiconductor, LMX2332USLBX Datasheet - Page 33

• Manufacturer Part Number: LMX2332USLBX
• Description: IC FREQ SYNTH DUAL 24LAMINATECSP
• Manufacturer: National Semiconductor
• Series: PLLatinum™r
• Type: PLL Frequency Synthesizerr

Specifications of LMX2332USLBX

• Pll: Yes with Bypass
• Input: CMOS, TTL
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: Yes/No
• Frequency - Max: 1.2GHz, 600MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-Laminate CSP
• Frequency-max: 1.2GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LMX2332USLBXTR

Test Setups
The block diagram above illustrates the setup required to
measure the LMX233xU device’s RF input sensitivity level.
The same setup is used for the LMX2330TMEB/
LMX2330SLEEB Evaluation Boards. The IF input sensitivity
test setup is similar to the RF sensitivity test setup. The
purpose of this test is to measure the acceptable signal level
to the f
signal range, the feedback divider begins to divide incor-
rectly and miscount the frequency.
The setup uses an open loop configuration. A power supply
is connected to V
is powered down (PWDN IF Bit = 1). By means of a signal
generator, an RF signal is applied to the f
pad provides a 50 Ω match between the PLL and the signal
generator. The OSC
typically set to 10000 in Code Loader, i.e. RF N_CNTRB
Word = 156 and RF N_CNTRA Word = 16 for PRE RF Bit =
1 (LMX2330U) or PRE RF = 0 (LMX2331U and LMX2332U).
The feedback divider output is routed to the F
IN
RF input of the PLL chip. Outside the acceptable
cc
and swept from 2.7V to 5.5V. The IF PLL
in
(Continued)
pin is tied to V
cc
IN
. The N value is
RF pin. The 3 dB
LMX233xU f
o
LD pin by
IN
Sensitivity Test Setup
33
selecting the RF PLL N Divider Output word (F
6 or 14) in Code Loader. A Universal Counter is connected to
the F
signal generator. The output of the feedback divider is thus
monitored and should be equal to f
The f
with the signal generator. The measurements are repeated
at different temperatures, namely T
+85˚C. Sensitivity is reached when the frequency error of the
divided RF input is greater than or equal to 1 Hz. The power
attenuation from the cable and the 3 dB pad must be ac-
counted for. The feedback divider will actually miscount if too
much or too little power is applied to the f
Therefore, the allowed input power level will be bounded by
the upper and lower sensitivity limits. In a typical application,
if the power level to the f
tivity limits, this can introduce spurs and degradation in
phase noise. When the power level gets even closer to these
limits, or exceeds it, then the RF PLL loses lock.
o
IN
LD pin and tied to the 10 MHz reference output of the
RF input frequency and power level are then swept
IN
RF input approaches the sensi-
IN
A
RF / N.
= -40˚C, +25˚C, and
IN
o
www.national.com
LD Word =
RF input.
10136640