ISL12030IBZ-T Intersil, ISL12030IBZ-T Datasheet - Page 12

• Manufacturer Part Number: ISL12030IBZ-T
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of ISL12030IBZ-T

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12030IBZ-TTR

Example 2
• Pulsed interrupt once per minute (IM = ”1”)
• Interrupts at one minute intervals when the seconds
• Set Alarm registers as follows:
Once the registers are set, the following waveform will be
seen at IRQ as shown in Figure 2:
Note that the status register ALM0 bit will be set each time
the alarm is triggered, but does not need to be read or
cleared.
User Memory Registers (accessed by
using Slave Address 1010111x)
Addresses [00h to 7Fh]
These registers are 128 bytes of user SRAM. Writes to this
section do not need to be proceeded by setting the WRTC
bit. Note that this memory, like the status and control
registers, is volatile and will be lost or corrupted when V
drops below 1.8V.
REGISTER
register is at 30 seconds.
ALARM
MNA0
MOA0
DWA0
SCA0
HRA0
DTA0
RTC AND ALARM REGISTERS ARE BOTH “30s”
7 6 5 4 3 2 1 0 HEX
1 0 1 1 0 0 0 0 B0h Seconds set to 30,
0 0 0 0 0 0 0 0 00h Minutes disabled
0 0 0 0 0 0 0 0 00h Hours disabled
0 0 0 0 0 0 0 0 00h Date disabled
0 0 0 0 0 0 0 0 00h Month disabled
0 0 0 0 0 0 0 0 00h Day of week disabled
FIGURE 2. IRQ WAVEFORM
BIT
60s
12
enabled
DESCRIPTION
DD
ISL12030
I
The ISL12030 supports a bi-directional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is the master
and the device being controlled is the slave. The master
always initiates data transfers and provides the clock for
both transmit and receive operations. Therefore, the
ISL12030 operates as a slave device in all applications.
All communication over the I
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 3). On power-up of the ISL12030, the SDA pin is in
the input mode.
All I
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL12030 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 3). A START condition is ignored during the power-up
sequence.
All I
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 3). A STOP condition at the end of
a read operation or at the end of a write operation to memory
only places the device in its standby mode.
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 4).
The ISL12030 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL12030 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
2
C Serial Interface
2
2
C interface operations must begin with a START
C interface operations must be terminated by a STOP
2
C interface is conducted by
January 15, 2008
FN6617.1