ISL12030IBZ-T Intersil, ISL12030IBZ-T Datasheet - Page 7

• Manufacturer Part Number: ISL12030IBZ-T
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of ISL12030IBZ-T

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12030IBZ-TTR

industry I
signal (SDA) and a clock signal (SCL).
Register Descriptions
The registers are accessible following an I
“1101 111x” and reads or writes to addresses [00h:47h]. The
defined addresses and default values are described in the
Table 1. The general purpose SRAM has a different slave
address (1010 111x), so it is not possible to read/write that
section of memory while accessing the registers.
REGISTER ACCESS
The contents of the registers can be modified by performing
a byte or a page write operation directly to any register
address.
The registers are divided into 5 sections. They are:
ADDR SECTION
1. Real Time Clock (8 bytes): Address 00h to 07h.
2. Status (1 bytes): Address 08h.
3. Control (2 bytes): 0Ch and 13h.
4. Day Light Saving Time (8 bytes): 15h to 1Ch
5. Alarm 0/1 (12 bytes):1Dh to 28h
0Ch
1Ah
1Bh
1Ch
1Dh
1Eh
00h
01h
02h
03h
04h
05h
06h
07h
08h
13h
15h
16h
17h
18h
19h
1Fh
20h
21h
22h
DSTCR
Control
Alarm0
2
Status
RTC
C serial bus protocols using a bi-directional data
TABLE 1. REGISTER MEMORY MAP (X indicates writes to these bits have no effect on the device)
DstDwFd
DstMoRv
DstDwRv
DstMoFd
DstHrFd
DstDtRv
DstHrRv
NAME
DstDtFd
SRDC
MOA0
DWA0
REG
MNA0
HRA0
SCA0
DTA0
MO
DW
INT
SC
MN
HR
YR
AC
DT
SS
HrFdMIL
HrRvMIL
AC5060
EMOA0
EDWA0
ESCA0
EMNA0
EHRA0
EDTA0
7
ARST
DSTE
YR23
MIL
0
0
0
0
0
0
0
0
0
0
0
0
7
DSTADJ
MNA021
SCA022
ACENB
DwFdE
DwRvE
WRTC
MN22
SC22
YR22
2
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C slave byte of
WkRv12
MNA020
HRA021
WkFd12
SCA021
DTA021
DtFd21
HrFd21
DtRv21
HrRv21
SC21
MN21
HR21
YR21
ALM1
DT21
IM
5
0
0
0
X
0
0
0
0
ISL12030
MOA020
MNA013
HRA020
MoFd20
WkFd11
MoRv20
WkRv11
SCA020
DTA020
HrRv20
DtFd20
HrFd20
DtRv20
MN20
MO20
SC20
HR20
YR20
ALM0
DT20
4
X
X
0
0
0
BIT
Write capability is allowable into the RTC registers (00h to
07h) only when the WRTC bit (bit 6 of address 0Ch) is set to
“1”. A multi-byte read or write operation is limited to one
section per operation. Access to another section requires a
new operation. A read or write can begin at any address
within the section.
A register can be read by performing a random read at any
address at any time. This returns the contents of that
register’s location. Additional registers are read by
performing a sequential read. For the RTC and Alarm
registers, the read instruction latches all clock registers into
a buffer, so an update of the clock does not change the time
being read. At the end of a read, the master supplies a stop
condition to end the operation and free the bus. After a read,
the address remains at the previous address +1 so the user
can execute a current address read and continue reading
the next register.
It is only necessary to set the WRTC bit prior to writing into
the RTC registers. All other registers are completely
accessible without setting the WRTC bit.
MNA012
MOA013
WkFd10
MoRv13
WkRv10
SCA013
HRA013
MoFd13
DTA013
HrRv13
DtFd13
HrFd13
DtRv13
MN13
MO13
SC13
HR13
DT13
YR13
SS3
3
X
X
0
0
0
MOA012
DwFd12
MoRv12
DwRv12
SCA012
MNA011
HRA012
MoFd12
DTA012
HrFd12
DtRv12
HrRv12
DWA02
DtFd12
MN12
MO12
SC12
HR12
DT12
YR12
DW2
SS2
2
X
X
0
MOA011
DwRv11
MNA011
HRA011
MoFd11
DwFd11
MoRv11
SCA011
DTA011
HrRv11
DWA01
DtFd11
HrFd11
DtRv11
MN11
MO11
SC11
HR11
YR11
ALE1
DT11
DW1
SS1
1
X
0
MNA010
MOA010
MoFd10
DwFd10
MoRv10
DwRv10
SCA010
HRA010
DTA010
DtFd10
HrFd10
DtRv10
HrRv10
DWA00
MN10
HR10
MO10
RTCF
SC10
DT10
YR10
ALE0
DW0
SS0
0
X
RANGE
0 to 59
0 to 59
0 to 23
1 to 12
1 to 31
1 to 12
1 to 31
1 to 12
0 to 99
0 to 23
1 to 31
0 to 23
0 to 59
0 to 59
0 to 23
1 to 31
1 to 12
0 to 6
0 to 9
0 to 6
0 to 6
0 to 6
N/A
N/A
N/A
January 15, 2008
DEFAULT
FN6617.1
00h
00h
00h
01h
01h
00h
00h
00h
01h
01h
00h
04h
00h
01h
02h
10h
00h
01h
02h
00h
00h
00h
01h
01h
00h