ISL12028IV27Z-T Intersil, ISL12028IV27Z-T Datasheet - Page 18

• Manufacturer Part Number: ISL12028IV27Z-T
• Description: IC RTC EEPROM LP 14-TSSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of ISL12028IV27Z-T

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12028IV27Z-TTR

condition can only be issued after the transmitting device
has released the bus (see Figure 17).
ACKNOWLEDGE
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting 8 bits.
During the ninth clock cycle, the receiver will pull the SDA
line LOW to acknowledge that it received the 8 bits of data
(see Figure 18).
The device will respond with an acknowledge after
recognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave Address
Byte. If a write operation is selected, the device will respond
with an acknowledge after the receipt of each subsequent
8-bit word. The device will not acknowledge if the slave
address byte is incorrect.
In the read mode, the device will transmit 8-bits of data,
release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will continue
to transmit data. The device will terminate further data
transmissions if an acknowledge is not detected. The master
FROM TRANSMITTER
FROM RECEIVER
DATA OUTPUT
DATA OUTPUT
SCL FROM
MASTER
SDA
SCL
SDA
SCL
18
FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER
START
FIGURE 16. VALID DATA CHANGES ON THE SDA BUS
FIGURE 17. VALID START AND STOP CONDITIONS
DATA STABLE
START
ISL12028, ISL12028A
1
DATA CHANGE
must then issue a stop condition to return the device to
Standby mode and place the device into a known state.
Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The first four bits of the Slave Address Byte
specify access to either the EEPROM array or to the CCR.
Slave bits ‘1010’ access the EEPROM array. Slave bits
‘1101’ access the CCR.
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the customer
to a known state.
Bit 3 through Bit 1 of the slave byte specify the device select
bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the operation
to be performed. When this R/W bit is a one, then a read
operation is selected. A zero selects a write operation. Refer
to Figure 19.
After loading the entire Slave Address Byte from the SDA
bus, the ISL12028 compares the device identifier and device
select bits with ‘1010111’ or ‘1101111’. Upon a correct
compare, the device outputs an acknowledge on the SDA
line.
DATA STABLE
8
STOP
ACKNOWLEDGE
9
November 30, 2010
FN8233.9