ISL12028IV27Z-T Intersil, ISL12028IV27Z-T Datasheet - Page 9

• Manufacturer Part Number: ISL12028IV27Z-T
• Description: IC RTC EEPROM LP 14-TSSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of ISL12028IV27Z-T

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12028IV27Z-TTR

Description
The ISL12028 device is a Real Time Clock with clock/calendar,
two polled alarms with integrated 512x8-bit EEPROM, oscillator
compensation, CPU Supervisor (Power-On-Reset, Low
Voltage Sensing and Watchdog Timer) and battery backup
switch.
The oscillator uses an external, low-cost 32.768kHz crystal.
All compensation and trim components are integrated on the
chip. This eliminates several external discrete components
and a trim capacitor, saving board area and component cost.
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes and Seconds. The Calendar has
separate registers for Date, Month, Year and Day-of-week.
The calendar is correct through 2099, with automatic leap
year correction.
The Dual Alarms can be set to any Clock/Calendar value for a
match. For instance, every minute, every Tuesday, or 5:23 AM
on March 21. The alarms can be polled in the Status Register
or can provide a hardware interrupt (IRQ/F
repeat mode for the alarms allowing a periodic interrupt.
The IRQ/F
frequency output of 1Hz, 4096Hz, or 32,768Hz or inactive.
The ISL12028 device integrates CPU Supervisory functions
(POR, WDT) and Battery Switch. There is Power-On-Reset
(RESET) output with 250ms delay from power on when the
V
will also assert RESET when V
V
selectable via VTS2/VTS1/VTS0 registers to five (5)
pre-selected levels. There is Watchdog Timer (WDT) with 3
selectable time-out periods (0.25s, 0.75s and 1.75s) and
disabled setting. The Watchdog Timer activates the RESET
pin when it expires. Normally, the I
when the RESET output is active, but this can be changed
by using a register bit to enable I
backup mode.
The device offers a backup power input pin. This V
allows the device to be backed up by battery or SuperCap.
The entire ISL12028 device is fully operational from 2.7 to
5.5V and the clock/calendar portion of the ISL12028 device
remains fully operational down to 1.8V (Standby Mode).
The ISL12028 device provides 4k bits of EEPROM with 8
modes of BlockLock™ control. The Block Lock allows a
safe, secure memory for critical user and configuration data,
while allowing a large user storage area.
Pin Descriptions
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device. The input buffer on this pin is always active (not
DD
RESET
supply crosses the V
threshold for the device. The V
OUT
pin may be software selected to provide a
RESET
9
DD
2
threshold for the device. It
C operation in battery
goes below the specified
2
C Interface is disabled
RESET
OUT
pin). There is a
threshold is
ISL12028, ISL12028A
BAT
pin
gated). The pull-up resistor on this pin must use the same
voltage source as V
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It has an open drain output and may be wire
ORed with other open drain or open collector outputs. The
input buffer is always active (not gated).
This open drain output requires the use of a pull-up resistor.
The pull-up resistor on this pin must use the same voltage
source as V
the output signal with the use of a slope controlled
pull-down. The circuit is designed for 400kHz I
speed.
V
This input provides a backup supply voltage to the device.
V
supply fails. This pin can be connected to a battery, a
SuperCap or tied to ground if not used.
Note that the device is not guaranteed to operate with
V
than this minimum, correct operation of the device,
(especially after a V
guaranteed.
IRQ/F
This dual function pin can be used as an interrupt or
frequency output pin. The IRQ/F
the frequency out control bits of the control/status register. It
has a CMOS push-pull output and can be used to clock
other devices and maintain low power dissipation.
• Interrupt Mode. The pin provides an interrupt signal
• Frequency Output Mode. The pin outputs a clock signal,
RESET
The RESET signal output can be used to notify a host
processor that the Watchdog timer has expired or the V
voltage supply has dipped below the V
an open drain, active LOW output. Recommended value for
the pull-up resistor is 5kΩ. If unused, it can be tied to ground.
In battery mode, the Watchdog timer function is disabled.
The RESET signal output is asserted LOW when the V
voltage supply has dipped below the V
the RESET signal output will not return HIGH until the device
is back to V
the V
X1, X2
The X1 and X2 pins are the input and output, respectively, of
an inverting amplifier. An external 32.768kHz quartz crystal is
BAT
BAT
BAT
output. This signal notifies a host processor that an alarm
has occurred and requests action.
which is related to the crystal frequency. The frequency
output is user selectable and enabled via the I
< 1.8V. If the battery voltage is expected to drop lower
DD
supplies power to the device in the event the V
OUT
voltage is above V
(Interrupt Output/Frequency Output)
DD
DD
. The output circuitry controls the fall time of
mode (out of Batttery Backup mode) even if
DD
DD
.
power-down cycle) is not
RESET
OUT
threshold.
mode is selected via
RESET
RESET
threshold. It is
threshold but
2
November 30, 2010
C interface
2
C.
DD
FN8233.9
DD
DD