ISL1219IUZ Intersil, ISL1219IUZ Datasheet

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... MARKING RANGE ISL1219IUZ 1219Z 2.7V to 5.5V - MSOP ISL1219IUZ-T* 1219Z 2.7V to 5.5V - MSOP *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...

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Block Diagram SDA SDA BUFFER SCL SCL BUFFER X1 CRYSTAL OSCILLATOR TRIP V BAT EVIN GND Pin Descriptions PIN NUMBER SYMBOL 1 X1 X1. The X1 pin is the input of an inverting amplifier and is ...

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Absolute Maximum Ratings Voltage SCL, SDA, and IRQ/F DD BAT (respect to ground ...

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I C Interface Specifications Test Conditions: V SYMBOL PARAMETER V SDA and SCL Input Buffer LOW IL Voltage V SDA and SCL Input Buffer HIGH IH Voltage Hysteresis SDA and SCL Input Buffer Hysteresis V SDA Output Buffer LOW ...

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I C Interface Specifications Test Conditions: V SYMBOL PARAMETER Rpu SDA and SCL Bus Pull-up Resistor Off-chip NOTES: 2. IRQ and F and EVDET Inactive. OUT 3. LPMODE = 0 (default order to ensure proper timekeeping, the ...

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Typical Performance Curves VDD 1E-6 900E-9 800E-9 700E-9 600E-9 500E-9 400E-9 300E-9 200E-9 100E-9 000E+0 1.5 2.0 2.5 3.0 3.5 4.0 V (V) BAT FIGURE BAT 2.4E-06 2.2E- 2.0E-06 1.8E-06 1.6E-06 V ...

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Typical Performance Curves 8.00E-06 7.00E-06 6.00E-06 5.00E-06 4.00E-06 3.00E-06 +85°C 2.00E-06 1.00E-06 0.00E-00 2.5 3.0 3.5 4 FIGURE 7. EVIN I PULL-UP EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR V 5.0V 1533Ω SDA AND IRQ/FOUT 100pF FIGURE 9. STANDARD ...

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... Functional Description Power Control Operation The power control circuit accepts a V Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power the ISL1219 for years. Another option is to use a Super Cap for applications where month. See the “ ...

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BATTERY BACKUP MODE BAT V TRIP V TRIP FIGURE 12. BATTERY SWITCHOVER WHEN V 2 The I C bus is deactivated in battery backup mode to provide lower power. Aside from this, all RTC functions are operational ...

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Event Detect Timing Diagram With Sampling Mode Enabled Case 1, Switched Opened Before I 15 CLKS (8x OFF OPEN EXT. SWITCH CLOSED HIGH EV IN LOW HIGH EVDET LOW 8 CLKS (8x) Case 2, Switched Opened After ...

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Accuracy of the Real Time Clock The accuracy of the Real Time Clock depends on the frequency of the quartz crystal that is used as the time base for the RTC. Since the resonant frequency of a crystal is temperature ...

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For the RTC and Alarm registers, the read instruction latches all clock registers into a buffer update of the clock does not change the time being read. A sequential read will not result in the output ...

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Real Time Clock Registers Addresses [00h to 06h] RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW) These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 0 to 59, HR (Hour) can ...

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AUTO RESET ENABLE BIT (ARST) This bit enables/disables the automatic reset of the BAT and ALM, EVT status bits only. When ARST bit is set to “1”, these status bits are reset to “0” after a valid read of the ...

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Slower sampling significantly reduces the supply current drain. TABLE 10. ESMP1 ESMP0 EVENT SAMPLING RATE EVENT INPUT TIME BASE HYSTERESIS SELECTION BITS (EHYS<1:0>) These two bits select the ...

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TABLE 12. BMATR1 BMATR0 0 0 0pF 0 1 -0.5pF (≈ +2ppm +0.5pF (≈ -2ppm +1pF (≈ -4ppm) DIGITAL TRIMMING REGISTER (DTR <2:0>) The digital trimming bits DTR0, DTR1, and DTR2 adjust the average number of ...

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Note: xx indicate other control bits After these registers are set, an alarm will be generated when the RTC advances to exactly 11:30am on January 1 (after seconds changes from 59 to 00) by setting the ALM bit in the ...

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SCL SDA START FIGURE 14. VALID DATA CHANGES, START, AND STOP CONDITIONS SCL FROM MASTER SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START FIGURE 15. ACKNOWLEDGE RESPONSE FROM RECEIVER SIGNALS FROM S THE MASTER T IDENTIFICATION A ...

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Device Addressing Following a start condition, the master must output a Slave Address Byte. The 7 MSBs are the device identifier. These bits are “1101111”. Slave bits “1101” access the register. Slave bits “111” specify the device select bits. The ...

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Application Section Event Detection The event detection feature of the ISL1219 is intended to be used for recording the time of single events that involve the opening of an enclosure, door, etc. The normal method of detection is with normally ...

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Battery Backup Details The event detection function has been designed to minimize power drain for extended life in battery backed applications. Many applications will need detection while in battery backup. Another bit, the EVBATB bit, is used to control if ...

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TEMPERATURE (°C) FIGURE 20. RTC CRYSTAL TEMPERATURE DRIFT If full industrial temperature compensation is desired in an ISL1219 ...

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These devices are available from such vendors as Panasonic and Murata. The main specifications include working voltage and leakage current. If the application is for charging the capacitor from a +5V ±5% supply with a signal diode, then ...

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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...