ISL12026IBZ Intersil, ISL12026IBZ Datasheet - Page 4

• Manufacturer Part Number: ISL12026IBZ
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of ISL12026IBZ

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Clock Format: HH
• Clock Ic Type: RTC
• Interface Type: I2C, Serial
• Memory Configuration: 512 X 8
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EEPROM Specifications
Serial Interface (I
DC Electrical Specifications
AC Electrical Specifications
Hysteresis SDA and SCL Input Buffer
SYMBOL
SYMBOL
SYMBOL
t
t
t
t
t
HD:STA
SU:DAT
HD:DAT
SU:STO
SU:STA
t
t
f
t
V
HIGH
LOW
V
I
t
BUF
V
SCL
t
I
LO
AA
IN
OL
LI
IH
IL
EEPROM Endurance
EEPROM Retention
SDA, and SCL Input Buffer LOW
Voltage
SDA, and SCL Input Buffer HIGH
Voltage
Hysteresis
SDA Output Buffer LOW Voltage
Input Leakage Current on SCL
I/O Leakage Current on SDA
SCL Frequency
Pulse width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free Before
the Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup Time
2
C) Specifications
PARAMETER
PARAMETER
PARAMETER
4
Temperature ≤75°C
I
V
V
Any pulse narrower than the max
spec is suppressed.
SCL falling edge crossing 30% of
V
70% of V
SDA crossing 70% of V
a STOP condition, to SDA
crossing 70% of V
following START condition.
Measured at the 30% of V
crossing.
Measured at the 70% of V
crossing.
SCL rising edge to SDA falling
edge. Both crossing 70% of V
From SDA falling edge crossing
30% of V
crossing 70% of V
From SDA exiting the 30% to
70% of V
edge crossing 30% of V
From SCL rising edge crossing
70% of V
30% to 70% of V
From SCL rising edge crossing
70% of V
crossing 30% of V
OL
IN
IN
DD
= 4mA
= 5.5V
= 5.5V
, until SDA exits the 30% to
TEST CONDITIONS
TEST CONDITIONS
TEST CONDITIONS
DD
DD
DD
DD
DD
window, to SCL rising
, to SDA rising edge
window.
to SCL falling edge
to SDA entering the
ISL12026
DD
DD
DD
DD
window.
.
.
during the
DD
DD
DD
DD
during
.
DD
.
>2,000,000
0.05 x V
0.7 x V
1300
1300
MIN
MIN
MIN
-0.3
600
600
600
100
600
50
0
0
DD
DD
TYP
TYP
TYP
100
100
V
0.3 x V
DD
MAX
MAX
MAX
400
900
0.4
50
+ 0.3
DD
UNITS
Cycles
UNITS
UNITS
Years
kHz
nA
nA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
V
V
October 23, 2006
NOTES
NOTES
NOTES
FN8231.5