M41T80M6E STMicroelectronics, M41T80M6E Datasheet - Page 10

• Manufacturer Part Number: M41T80M6E
• Description: IC RTC SERIAL W/ALARM 8-SOIC
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/Alarmr

Specifications of M41T80M6E

• Memory Size: 20B
• Time Format: HH:MM:SS:hh (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Function: Clock/Calendar/Alarm/Timer Interrupt
• Rtc Memory Size: 20 Byte
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial (2-Wire, I2C)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2820-5; M41T80M6

Operation
2.2
Note:
10/25
Table 2.
1. Valid for ambient operating temperature: T
2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of
READ mode
In this mode the master reads the M41T80 slave after setting the slave address
READ mode
acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the
START condition and slave address are repeated followed by the READ mode control bit
(R/W=1). At this point the master transmitter becomes the master receiver. The data byte
which was addressed will be transmitted and the master receiver will send an acknowledge
bit to the slave transmitter. The address pointer is only incremented on reception of an
acknowledge clock. The M41T80 slave transmitter will now place the data byte at address
An+1 on the bus, the master receiver reads and acknowledges the new byte and the
address pointer is incremented to “An+2.”
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume due to a stop condition or when the
pointer increments to any non-clock address (08h-13h).
This is true both in READ mode and WRITE mode.
An alternate READ mode may also be implemented whereby the master reads the M41T80
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see
t
noted).
the falling edge of SCL.
SU:DAT
t
t
t
t
SU:STO
HD:STA
SU:STA
HD:DAT
t
Sym
t
f
t
HIGH
LOW
BUF
SCL
t
t
R
F
(2)
AC characteristics
sequence). Following the WRITE mode control bit (R/W=0) and the
SCL clock frequency
Clock low period
Clock high period
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
(after this period the first clock pulse is generated)
START condition setup time
(only relevant for a repeated start condition)
Data setup time
Data hold time
STOP condition setup time
Time the bus must be free before a new
transmission can start
Doc ID 9074 Rev 4
Parameter
Figure 9: Alternative READ mode
A
(1)
= –40 to 85 °C; V
CC
= 2.0 to 5.5 V (except where
Min
600
600
600
100
600
1.3
1.3
0
0
sequence).
Typ
Max
400
300
300
(Figure 8:
M41T80
Units
kHz
µs
ns
ns
ns
ns
ns
ns
µs
ns
µs