ISL12024IRTCZ Intersil, ISL12024IRTCZ Datasheet - Page 18

• Manufacturer Part Number: ISL12024IRTCZ
• Description: IC RTC/CALENDER 64BIT 8-TDFN
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of ISL12024IRTCZ

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TDFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Acknowledge Polling
Disabling of the inputs during non-volatile write cycles can
be used to take advantage of the 12ms (typ) write cycle time.
Once the stop condition is issued to indicate the end of the
master’s byte load operation, the ISL12024IRTCZ initiates
the internal non-volatile write cycle. Acknowledge polling can
begin immediately. To do this, the master issues a start
condition followed by the Memory Array Slave Address Byte
for a write or read operation (AEh or AFh). If the
ISL12024IRTCZ is still busy with the non-volatile write cycle
then no ACK will be returned. When the ISL12024IRTCZ has
completed the write operation, an ACK is returned and the
host can proceed with the read or write operation. See the
flow chart in Figure 20. Note: Do not use the CCR Slave byte
(DEh or DFh) for Acknowledge Polling.
Read Operations
There are three basic read operations: Current Address
Read, Random Read and Sequential Read.
CURRENT ADDRESS READ
Internally the ISL12024IRTCZ contains an address counter
that maintains the address of the last word read incremented
by one. Therefore, if the last read was to address n, the next
read operation would access data from address n + 1. On
power-up, the 16-bit address is initialized to 00h. In this way,
SIGNALS FROM
SIGNALS FROM
THE MASTER
SDA BUS
THE SLAVE
ADDRESS POINTER ENDS
6 BYTES
FIGURE 17. WRITING 12 BYTES TO A 16-BYTE MEMORY PAGE STARTING AT ADDRESS 10
ADDRESS = 5
AT ADDR = 5
S
T
A
R
T
18
1
ADDRESS
SLAVE
1
1
1
0
A
C
K
FIGURE 18. PAGE WRITE SEQUENCE
0 0 0 0 0 0 0
ADDRESS 1
WORD
ISL12024IRTCZ
A
C
K
ADDRESS 0
a current address read immediately after the power-on reset
can download the entire contents of memory starting at the
first location. Upon receipt of the Slave Address Byte with
the R/W bit set to one, the ISL12024IRTCZ issues an
acknowledge, then transmits 8 data bits. The master
terminates the read operation by not responding with an
acknowledge during the ninth clock and issuing a stop
condition. See Figure 19 for the address, acknowledge, and
data transfer sequence.
ADDRESS
WORD
SIGNALS FROM
SIGNALS FROM
10
THE MASTER
SDA BUS
FIGURE 19. CURRENT ADDRESS READ SEQUENCE
THE SLAVE
A
C
K
1 ≤ n ≤ 16 for EEPROM array
1 ≤ n ≤ 8 for CCR
DATA
(1)
6 BYTES
S
T
A
R
T
1
ADDRESS
SLAVE
ADDRESS
1
1
15
1
1
DATA
(n)
A
C
K
DATA
A
C
K
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August 8, 2008
FN6749.0
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