ISL12024IRTCZ Intersil, ISL12024IRTCZ Datasheet - Page 4

• Manufacturer Part Number: ISL12024IRTCZ
• Description: IC RTC/CALENDER 64BIT 8-TDFN
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of ISL12024IRTCZ

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TDFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC Electrical Specifications
Serial Interface (I
DC Electrical Specifications
EEPROM Specifications
EEPROM Endurance
EEPROM Retention
SYMBOL
Hysteresis SDA and SCL Input Buffer Hysteresis
SYMBOL
t
t
t
t
t
t
HD:STO
HD:STA
SU:DAT
HD:DAT
SU:STO
SU:STA
t
t
t
f
HIGH
LOW
SCL
t
BUF
t
V
t
V
AA
DH
V
I
IN
I
LO
OL
LI
IH
IL
SCL Frequency
Pulse width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free Before
the Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Set-up Time
START Condition Hold Time
Input Data Set-up Time
Input Data Hold Time
STOP Condition Set-up Time
STOP Condition Hold Time for
Read, or Volatile Only Write
Output Data Hold Time
SDA, and SCL Input Buffer LOW
Voltage
SDA, and SCL Input Buffer HIGH
Voltage
SDA Output Buffer LOW Voltage
Input Leakage Current on SCL
I/O Leakage Current on SDA
PARAMETER
PARAMETER
PARAMETER
2
C) Specifications
4
Temperature ≤ +75°C
Any pulse narrower than the max spec is
suppressed.
SCL falling edge crossing 30% of V
SDA exits the 30% to 70% of V
SDA crossing 70% of V
condition, to SDA crossing 70% of V
the following START condition.
Measured at the 30% of V
Measured at the 70% of V
SCL rising edge to SDA falling edge. Both
crossing 70% of V
From SDA falling edge crossing 30% of V
SCL falling edge crossing 70% of V
From SDA exiting the 30% to 70% of V
window, to SCL rising edge crossing 30% of
V
From SCL rising edge crossing 70% of V
SDA entering the 30% to 70% of V
From SCL rising edge crossing 70% of V
SDA rising edge crossing 30% of V
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
From SCL falling edge crossing 30% of V
until SDA enters the 30% to 70% of V
window.
DD
I
V
V
OL
.
IN
IN
TEST CONDITIONS
= 4mA
TEST CONDITIONS
= 5.5V
= 5.5V
ISL12024IRTCZ
TEST CONDITIONS
DD
DD
.
.
DD
DD
DD
during a STOP
crossing.
crossing.
DD
0.05 x V
window.
DD
0.7 x V
DD
(Note 12)
DD
DD
DD
DD
MIN
-0.3
window.
.
, until
.
DD
0
during
2,000,000
DD
DD
DD
DD
DD
DD
MIN
, to
50
,
to
to
(Note 12)
TYP
100
100
1300
1300
MIN
600
600
600
100
600
600
0
0
TYP
V
(Note 12)
0.3 x V
TYP
DD
MAX
0.4
+ 0.3
(Note 12) UNITS NOTES
DD
MAX
400
900
MAX
50
UNITS
nA
nA
V
V
V
V
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
August 8, 2008
UNITS
Cycles
Years
NOTES
9, 11
FN6749.0