ISL12029IV27AZ Intersil, ISL12029IV27AZ Datasheet - Page 18

• Manufacturer Part Number: ISL12029IV27AZ
• Description: IC RTC/CALENDAR EEPROM 14-TSSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of ISL12029IV27AZ

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

operations. See “I
Backup and LVR Operation” on page 25.
In battery mode, the RESET signal output is asserted LOW
when the V
threshold. The RESET signal output will not return HIGH
until the device is back to V
above V
Serial Communication
The device supports the I
CLOCK AND DATA
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions (see Figure 16).
START CONDITION
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met (see Figure 17).
RESET
DD
FROM TRANSMITTER
voltage supply has dipped below the V
threshold.
FROM RECEIVER
2
C Communications During Battery
DATA OUTPUT
DATA OUTPUT
SCL FROM
MASTER
2
C bidirectional serial bus protocol.
SDA
SCL
DD
SDA
SCL
18
mode even the V
FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER
START
FIGURE 16. VALID DATA CHANGES ON THE SDA BUS
FIGURE 17. VALID START AND STOP CONDITIONS
DATA STABLE
DD
START
ISL12029, ISL12029A
voltage is
RESET
1
DATA CHANGE
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
condition can only be issued after the transmitting device
has released the bus (see Figure 17).
ACKNOWLEDGE
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting 8-bits.
During the ninth clock cycle, the receiver will pull the SDA
line LOW to acknowledge that it received the 8-bits of data
(refer to Figure 18).
The device will respond with an acknowledge after recognition
of a start condition and if the correct Device Identifier and Select
bits are contained in the Slave Address Byte. If a write
operation is selected, the device will respond with an
acknowledge after the receipt of each subsequent 8-bit word.
The device will not acknowledge if the slave address byte is
incorrect.
DATA STABLE
8
STOP
ACKNOWLEDGE
9
December 16, 2010
FN6206.10