ISL12029IV27AZ Intersil, ISL12029IV27AZ Datasheet - Page 21

• Manufacturer Part Number: ISL12029IV27AZ
• Description: IC RTC/CALENDAR EEPROM 14-TSSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of ISL12029IV27AZ

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

.
Acknowledge Polling
Disabling of the inputs during non-volatile write cycles can
be used to take advantage of the typical 5ms write cycle
time. Once the stop condition is issued to indicate the end of
the master’s byte load operation, the ISL12029 initiates the
internal non-volatile write cycle. Acknowledge polling can
begin immediately. To do this, the master issues a start
condition followed by the Memory Array Slave Address Byte
for a write or read operation (AEh or AFh). If the ISL12029 is
still busy with the non-volatile write cycle then no ACK will be
returned. When the ISL12029 has completed the write
operation, an ACK is returned and the host can proceed with
the read or write operation. Refer to the flow chart in
Figure 24. Note: Do not use the CCR Slave byte (DEh or
DFh) for Acknowledge Polling.
Read Operations
There are three basic read operations: Current Address
Read, Random Read and Sequential Read.
Current Address Read
Internally the ISL12029 contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n + 1. On
power-up, the 16-bit address is initialized to 0h. In this way, a
current address read immediately after the power-on reset
can download the entire contents of memory starting at the
first location. Upon receipt of the Slave Address Byte with
the R/W bit set to one, the ISL12029 issues an
acknowledge, then transmits 8 data bits. The master
terminates the read operation by not responding with an
acknowledge during the ninth clock and issuing a stop
condition. Refer to Figure 23 for the address, acknowledge,
and data transfer sequence.
SIGNALS FROM
SIGNALS FROM
THE MASTER
SDA BUS
THE SLAVE
A
R
S
T
T
21
1
ADDRESS
SLAVE
1
1
1
0
A
C
K
FIGURE 22. PAGE WRITE SEQUENCE
0 0 0 0 0 0 0
ISL12029, ISL12029A
ADDRESS 1
WORD
A
C
K
ADDRESS 0
SIGNALS FROM
SIGNALS FROM
THE MASTER
WORD
FIGURE 23. CURRENT ADDRESS READ SEQUENCE
THE SLAVE
CYCLE COMPLETE. CONTINUE
FIGURE 24. ACKNOWLEDGE POLLING SEQUENCE
SDA BUS
ISSUE MEMORY ARRAY SLAVE
AFH (READ) OR AEH (WRITE)
COMMAND SEQUENCE?
ENTER ACK POLLING
NON-VOLATILE WRITE
NORMAL READ OR
A
C
K
WRITE COMMAND
COMPLETED BY
RETURNED?
ISSUING STOP.
ISSUE START
1 ≤ n ≤ 16 FOR EEPROM ARRAY
1 ≤ n ≤ 8 FOR CCR
SEQUENCE
CONTINUE
BYTE LOAD
S
A
R
DATA
T
T
PROCEED
ADDRESS BYTE
(1)
1
YES
YES
ACK
ADDRESS
SLAVE
1
1
1
NO
NO
1
A
C
K
DATA
(n)
ISSUE STOP
DATA
December 16, 2010
A
C
K
ISSUE STOP
S
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P
T
FN6206.10
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