X1228S14 Intersil, X1228S14 Datasheet - Page 11

• Manufacturer Part Number: X1228S14
• Description: IC RTC CPU SUP WDT 4K EE 14-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of X1228S14

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
separate from the EEPROM array and are only
accessible following a slave byte of “1101111x” and
reads or writes to addresses [0000h:003Fh]. The
clock/control memory map has memory addresses
from 0000h to 003Fh. The defined addresses are
described in the Table 1. Writing to and reading from
the undefined addresses are not recommended.
CCR access
The contents of the CCR can be modified by perform-
ing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (4 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
Table 1. Clock/Control Memory Map
Addr.
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
(EEPROM)
(SRAM)
Control
Status
Type
RTC
Name
DTR
Y2K
ATR
Reg
DW
MO
INT
HR
MN
SR
YR
DT
SC
BL
11
BAT
Y23
BP2
MIL
IM
0
0
0
0
0
0
0
0
7
AL1E
M22
BP1
AL1
Y22
S22
6
0
0
0
0
0
0
0
Y2K21
ATR5
AL0E
M21
AL0
Y21
D21
H21
S21
BP0
5
0
0
0
Y2K20
ATR4
X1228
WD1
G20
M20
FO1
Y20
D20
H20
S20
0
4
0
0
Bit
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read.
The read instruction latches all Clock registers into a
buffer, so an update of the clock does not change the
time being read. A sequential read of the CCR will not
result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition
to end the operation and free the bus. After a read of
the CCR, the address remains at the previous address
+1 so the user can execute a current address read of
the CCR and continue reading the next Register.
ALARM REGISTERS
There are two alarm registers whose contents mimic
the contents of the RTC register, but add enable bits
and exclude the 24 hour time selection bit. The enable
bits specify which registers to use in the comparison
between the Alarm and Real Time Registers. For
example:
– Setting the Enable Month bit (EMOn*) bit in combi-
*n = 0 for Alarm 0: N = 1 for Alarm 1
Y2K13
ATR3
WD0
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
M13
FO0
Y13
G13
D13
H13
S13
3
0
0
0
RWEL
DTR2
ATR2
DY2
G12
M12
Y12
D12
H12
S12
2
0
x
0
DTR1
ATR1
WEL
DY1
G11
D11
H11
M11
Y11
S11
0
x
0
1
0 (optional)
Y2K10
RTCF
DTR0
ATR0
DY0
G10
M10
Y10
D10
H10
S10
x
0
Range
19/20
0-99
1-12
1-31
0-23
0-59
0-59
0-6
May 18, 2006
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FN8100.4