DS1486-120+ Maxim Integrated Products, DS1486-120+ Datasheet - Page 6

• Manufacturer Part Number: DS1486-120+
• Description: IC TIMEKEEPER RAM 128K 32-EDIP
• Manufacturer: Maxim Integrated Products
• Type: Watchdog Timer/NVSRAMr

Specifications of DS1486-120+

• Memory Size: 1M (128K x 8)
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 32-DIP Module (600 mil), 32-EDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS1486/DS1486P
TIME-OF-DAY REGISTERS
Registers 0, 1, 2, 4, 6, 8, 9, and A contain Time-of-Day data in BCD. Ten bits within these eight registers
are not used and will always read 0 regardless of how they are written. Bits 6 and 7 in the Months
Register (9) are binary bits. When set to logic 0, EOSC (Bit 7) enables the real-time clock oscillator. This
bit is set to logic 1 as shipped from Dallas Semiconductor to prevent lithium energy consumption during
storage and shipment (DIP Module only). This bit will normally be turned on by the user during device
initialization. However, the oscillator can be turned on and off as necessary by setting this bit to the
appropriate level. The INTA and Square Wave Output signals are tied together at pin 30 on the 32-pin
DIP module. With this package, ESQW (Bit 6) of the Months Register (9) controls the function of this
pin. When set to logic 0, the pin will output a 1024 Hz square wave signal. When set to logic 1, the pin is
available for interrupt A output (INTA) only. The INTA and Square Wave Output signals are separated
on the 34-pin PowerCap module. With this package, ESQW controls only the Square Wave Output (pin
33). When set to logic 0, pin 33 will output a 1024 Hz square wave signal. When set to logic 1, pin 33 is
in a high impedance state. Pin 34 (INTA) is not affected by the setting of bit 6. Bit 6 of the Hours register
is defined as the 12- or 24-hour select bit. When set to logic 1, the 12-hour format is selected. In the 12-
hour format, bit 5 is the AM/PM bit with logic 1 being PM. In the 24-hour mode, bit 5 is the second 10-
hour bit (20-23 hours). The Time-of-Day registers are updated every 0.01 seconds from the real-time
clock, except when the TE bit (bit 7 of Register B) is set low or the clock oscillator is not running. The
preferred method of synchronizing data access to and from the RAMified Timekeeper is to access the
Command register by doing a write cycle to address location B and setting the TE bit (Transfer Enable
bit) to a logic 0. This will freeze the External Time-of-Day registers at the present recorded time,
allowing access to occur without danger of simultaneous update. When the watch registers have been read
or written, a second write cycle to location B setting the TE bit to a logic 1 will put the Time-of-Day
Registers back to being updated every 0.01 second. No time is lost in the real-time clock because the
internal copy of the Time-of-Day register buffers is continually incremented while the external memory
registers are frozen. An alternate method of reading and writing the Time-of-Day registers is to ignore
synchronization. However, any single reading may give erroneous data as the real-time clock may be in
the process of updating the external memory registers as data is being read. The internal copies of seconds
through years are incremented and the Time-of-Day Alarm is checked during the period that hundreds of
seconds reads 99. The copies are transferred to the external register when hundredths of seconds roll from
99 to 00. A way of making sure data is valid is to do multiple reads and compare. Writing the registers
can also produce erroneous results for the same reasons. A way of making sure that the write cycle has
caused a proper update is to perform read verifies and re-execute the write cycle if data is not correct.
While the possibility of erroneous results from read and write cycles has been stated, it is worth noting
that the probability of an incorrect result is kept to a minimum due to the redundant structure of the
RAMified Timekeeper.
TIME-OF-DAY ALARM REGISTERS
Registers 3, 5, and 7 contain the Time-of-Day Alarm Registers. Bits 3, 4, 5, and 6 of Register 7 will
always read 0 regardless of how they are written. Bit 7 of Registers 3, 5, and 7 are mask bits (Figure 3).
When all of the mask bits are logic 0, a Time-of-Day Alarm will only occur when Registers 2, 4, and 6
match the values stored in Registers 3, 5, and 7. An alarm will be generated every day when bit 7 of
Register 7 is set to a logic 1. Similarly, an alarm is generated every hour when bit 7 of Registers 7 and 5
is set to a logic 1. When bit 7 of Registers 7, 5, and 3 is set to a logic 1, an alarm will occur every minute
when Register 1 (seconds) rolls from 59 to 00.
Time-of-Day Alarm Registers are written and read in the same format as the Time-of-Day Registers. The
Time-of-Day Alarm Flag and Interrupt are always cleared when Alarm Registers are read or written.
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