DS1486-120+ Maxim Integrated Products, DS1486-120+ Datasheet - Page 9

• Manufacturer Part Number: DS1486-120+
• Description: IC TIMEKEEPER RAM 128K 32-EDIP
• Manufacturer: Maxim Integrated Products
• Type: Watchdog Timer/NVSRAMr

Specifications of DS1486-120+

• Memory Size: 1M (128K x 8)
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 32-DIP Module (600 mil), 32-EDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS1486/DS1486P
COMMAND REGISTER (0Bh)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TE
IPSW
IBH/LO
PU/LVL
WAM
TDM
WAF
TDF
Bit 7: Transfer Enable (TE). This bit when set to a logic 0 will disable the transfer of data between
internal and external clock registers. The contents in the external clock registers are now frozen and reads
or writes will not be affected with updates. This bit must be set to a logic 1 to allow updates.
Bit 6: Interrupt Switch (IPSW). When set to a logic 1, INTA is the Time-of-Day Alarm and INTB
(INTB) is the Watchdog Alarm. When set to logic 0, this bit reverses the output pins. INTA is now the
Watchdog Alarm output and INTB (INTB) is the Time-of-Day Alarm output. The INTA/SQW output pin
shares both the interrupt A and square-wave output function. INTA and the square wave function should
never be simultaneously enabled or a conflict may occur (32-pin DIP module only).
Bit 5: Interrupt B Sink or Source Current (IBH/LO). When this bit is set to a logic 1 and V
is
CC
applied, INTB (INTB) will source current (see DC characteristics IOH). When this bit is set to a logic 0,
INTB will sink current (see I
in the DC Characteristics).
OL
Bit 4: Interrupt Pulse Mode or Level Mode (PU/LVL). This bit determines whether both interrupts
will output a pulse or level signal. When set to a logic 0, INTA and INTB (INTB) will be in the level
mode. When this bit is set to a logic 1, the pulse mode is selected and INTA will sink current for a
minimum of 3ms and then release. INTB (INTB) will either sink or source current, depending on the
condition of Bit 5, for a minimum of 3ms and then release. INTB will only source current when there is a
voltage present on V
.
CC
Bit 3: Watchdog Alarm Mask (WAM). When this bit is set to a logic 0, the Watchdog Interrupt output
will be activated. The activated state is determined by bits 1, 4, 5, and 6 of the Command Register. When
this bit is set to a logic 1, the Watchdog interrupt output is deactivated.
Bit 2: Time-of-Day Alarm Mask (TDM). When this bit is set to a logic 0, the Time-of-Day Alarm
Interrupt output will be activated. The activated state is determined by bits 0, 4, 5, and 6 of the Command
Register. When this bit is set to a logic 1, the Time-of-Day Alarm interrupt output is deactivated.
Bit 1: Watchdog Alarm Flag (WAF). This bit is set to a logic 1 when a watchdog alarm interrupt
occurs. This bit is read only. The bit is reset when any of the Watchdog Alarm registers are accessed.
When the interrupt is in the pulse mode (see bit 4 definition), this flag will be in the logic 1 state only
during the time the interrupt is active.
Bit 0: Time-of-Day Flag (TDF). This is a read-only bit. This bit is set to a logic 1 when a Time-of-Day
alarm has occurred. The time the alarm occurred can be determined by reading the Time-of-Day Alarm
registers. This bit is reset to a logic 0 state when any of the Time-of-Day Alarm registers are accessed.
When the interrupt is in the pulse mode (see bit 4 definition), this flag will be in the logic 1 state only
during the time the interrupt is active.
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