CS5513-BSZ Cirrus Logic Inc, CS5513-BSZ Datasheet - Page 11

IC ADC 20BIT INTERNAL OSC 8SOIC

CS5513-BSZ

Manufacturer Part Number
CS5513-BSZ
Description
IC ADC 20BIT INTERNAL OSC 8SOIC
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS5513-BSZ

Data Interface
Serial
Number Of Bits
20
Sampling Rate (per Second)
326
Number Of Converters
1
Power Dissipation (max)
2.7mW
Voltage Supply Source
Dual ±
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.200", 5.30mm Width)
Resolution (bits)
20bit
Sampling Rate
100SPS
Input Channel Type
Differential
Supply Voltage Range - Analog
4.75V To 5.25V
Supply Current
385µA
Digital Ic Case Style
SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
598-1707

Available stocks

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Quantity
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Quantity:
20 000
CS5512/13. The CS5510/11 follow the same
curve, but are limited to 16 bits of resolution. Note
that the reference voltage should not be estab-
lished prior to having the supply voltages on the V+
and V- pins.
2.2.1
Figure 5 illustrates the input model for the VREF
pin. It includes a coarse/fine charge buffer which
reduces the dynamic current demand of the exter-
DS337F4
Figure 4. CS5512/13 Measured Noise-Free Bits vs.
17
16
15
14
13
0
0.5
Voltage Reference Input Model
1
1.5
V
i = f V
o s
2
VREF.
n
VREF (V)
≤ 2 5 mV
VREF
2.5
o s
3
C
3.5
Figure 5. Input model for VREF pin.
4
f = 32.768 kHz
4.5
5
φ
nal reference. Typical CVF (sampling) current is
about 6 nA (See Figure 5).
The nominal input span of the converter is defined
to be a bipolar span equal to ±(VREF - V-)*(0.80
±0.08).
2.3
The CS5510/11/12/13 are designed to operate
from single or dual supplies. Figure 6 illustrates the
CS5510/11/12/13 connected with a single +5 V
supply to measure differential inputs relative to a
common mode of 2.5 V. Figure 7 illustrates the
CS5510/11/12/13 connected with ±2.5 V analog
supplies to measure ground-referenced, bipolar
signals. It is not necessary that the dual supples on
the ADCs be balanced, however, they must sum to
five volts. Figure 8 illustrates the ADCs configured
with V+ = +3.3 V and V- = -1.7 V, accommodating
a +3.3 V digital supply.
2.3.1
The many power supply configurations available in
the CS5510/11/12/13 allow for a wide range of dig-
ital logic levels. The logic-high input and output lev-
els are determined by the V+ pin. The logic-low
output on SDO is referenced to and driven by the
current logic-low voltage on CS. Since the
CS5510/11/12/13 do not include a dedicated
2
φ
Coarse
1
C = 7 p F
Fine
Power Supply Arrangements
Digital Logic Levels
CS5510/11/12/13
11

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