CS5513-BSZ Cirrus Logic Inc, CS5513-BSZ Datasheet - Page 20

• Manufacturer Part Number: CS5513-BSZ
• Description: IC ADC 20BIT INTERNAL OSC 8SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5513-BSZ

• Data Interface: Serial
• Number Of Bits: 20
• Sampling Rate (per Second): 326
• Number Of Converters: 1
• Power Dissipation (max): 2.7mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.200", 5.30mm Width)
• Resolution (bits): 20bit
• Sampling Rate: 100SPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 385µA
• Digital Ic Case Style: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1707

priate time during the third conversion cycle to en-
sure the maximum possible throughput.
2.6
The CS5510/11/12/13 exhibit excellent linearity
with low offset and gain drift, without the need for
calibration. If precision voltage measurements are
required by the system, however, software-based
offset and gain calibration can be performed by the
system.
To perform a software offset calibration, the “zero-
point” of the system should be established by ap-
plying an input to the system equal to zero. Then,
the user can obtain a conversion and store it in
memory as the system’s zero point (ZP). This num-
ber can then be used as the zero point for any sub-
sequent conversion words. In the 20-bit devices
(CS5512 and CS5513), multiple conversions can
be averaged to arrive at a more accurate offset val-
ue. In the 16-bit devices (CS5510 and CS5511),
averaging may not be meaningful, because the
noise will be below the size of one LSB when using
nominal voltages for VREF (2.5 V).
A software gain calibration can be performed by
bringing the system to a known calibration Voltage
value (Vcal) and acquiring a conversion (note that
Vcal should be low enough to compensate for the
possible gain error of the ADC). Multiple conver-
sions can be averaged at this point to improve the
accuracy of the calibration. The code obtained
from this conversion is the real value (Cr) of the
calibration Voltage input, and will differ from the
ideal value. The ideal value for this conversion (Ci)
20
Digital Off-chip System
Calibration
will be equivalent to: 0x7FFF*Vcal/(0.80*Vref) for
the CS5510/11, and 0x7FFFF*Vcal/(0.80*Vref) for
the CS5512/13. The gain error (GE) is equal to: (Cr
- ZP)/Ci. To correct for both offset and gain error in
subsequent conversions, subtract the offset error,
and then divide by the gain error.
2.7
The CS5510/11/12/13 accommodates two power
modes: normal and sleep. The normal mode is the
default mode and is entered after power is estab-
lished to the ADC. In normal mode, the ADCs typ-
ically consumes 2.5 mW. Sleep is entered when
the user leaves SCLK high for at least 200 μs. The
ADCs are guaranteed to be in sleep after SCLK is
high (logic 1) for 2 ms. The sleep mode reduces
the consumed power to less than 10 μW when CS
is high (logic 1). If CS is low (logic 0) at this time,
the SDO drive logic will still be active, and the con-
sumed sleep power will be greater. To exit sleep
and return to normal mode, the user must return
SCLK low for at least 10 μs. After a sleep is exited,
the ADCs reset all their internal logic, including
their digital filters, and begin performing conver-
sions. Since the filters are reset, the first three con-
version after returning to normal mode will not be
fully settled.
2.8
The CS5510/11/12/13 should be placed entirely
over the analog ground. Place the analog-digital
plane split immediately adjacent to the digital pins
of the chip.
Power Consumption, Sleep and
Reset
PCB Layout
CS5510/11/12/13
DS337F4