CS5530-ISZ Cirrus Logic Inc, CS5530-ISZ Datasheet - Page 25

• Manufacturer Part Number: CS5530-ISZ
• Description: IC ADC 24BIT 1CH W/LNA 20SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5530-ISZ

• Number Of Converters: 1
• Package / Case: 20-SSOP
• Number Of Bits: 24
• Sampling Rate (per Second): 3.84k
• Data Interface: Serial
• Power Dissipation (max): 45mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Architecture: Delta-Sigma
• Conversion Rate: 6.25 SPs to 3840 SPs
• Resolution: 24 bit
• Input Type: Voltage
• Interface Type: Serial (3-Wire)
• Voltage Reference: 2.5 V
• Maximum Power Dissipation: 500 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1158 - BOARD EVAL FOR CS5530
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1283-5

2.6 Using Multiple ADCs Synchronously
Some applications require synchronous data out-
puts from multiple ADCs converting different ana-
log channels. Multiple CS5530 devices can be
synchronized in a single system by using the fol-
lowing guidelines:
1) All of the ADCs in the system must be operated
from the same oscillator source.
2) All of the ADCs in the system must share com-
mon SCLK and SDI lines.
3) A software reset must be performed at the same
time for all of the ADCs after system power-up (by
selecting all of the ADCs using their respective CS
pins, and writing the reset sequence to all parts, us-
ing SDI and SCLK).
4) A start conversion command must be sent to all
of the ADCs in the system at the same time. The ±
8 clock cycles of ambiguity for the first conversion
(or for a single conversion) will be the same for all
ADCs, provided that they were all reset at the same
time.
5) Conversions can be obtained by monitoring
SDO on only one ADC, (bring CS high for all but
one part) and reading the data out of each part indi-
vidually, before the next conversion data words are
ready.
An example of a synchronous system using two
CS5530 devices is shown in Figure 12.
2.7 Conversion Output Coding
The CS5530 outputs 24-bit data conversion words.
To read a conversion word the user must read the
conversion data register. The conversion data reg-
ister is 32 bits long and outputs the conversions
MSB first. The last byte of the conversion data reg-
ister contains an overflow flag bit. The overrange
flag (OF) monitors to determine if a valid conver-
sion was performed.
DS742F3
The CS5530 output data conversions in binary for-
mat when operating in unipolar mode and in two's
complement when operating in bipolar mode. Ta-
ble 3 shows the code mapping for both unipolar and
bipolar modes. VFS in the tables refers to the posi-
tive full-scale voltage range of the converter in the
specified gain range, and -VFS refers to the nega-
tive full-scale voltage range of the converter. The
total differential input range (between AIN+ and
AIN-) is from 0 to VFS in unipolar mode, and from
-VFS to VFS in bipolar mode.
>(VFS-1.5 LSB) FFFFFF >(VFS-1.5 LSB)
Unipolar Input
VFS/2-0.5 LSB 800000
VFS-1.5 LSB
<(+0.5 LSB)
+0.5 LSB
CS5530
CS5530
Voltage
OSC2
OSC2
SCLK
Figure 12. Synchronizing Multiple ADCs
SCLK
SDO
SDO
SDI
SDI
CS
CS
Table 3. Output Coding
FFFFFF
FFFFFE
7FFFFF
000001
000000
000000 <(-VFS+0.5 LSB)
Binary
Offset
------
------
------
-VFS+0.5 LSB
Bipolar Input
VFS-1.5 LSB
-0.5 LSB
Voltage
SOURCE
CLOCK
μC
Complement
CS5530
7FFFFE
FFFFFF
7FFFFF
7FFFFF
000000
800001
800000
800000
Two's
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