CS5524-ASZ Cirrus Logic Inc, CS5524-ASZ Datasheet - Page 16

• Manufacturer Part Number: CS5524-ASZ
• Description: IC ADC 24BIT 4CH 20SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5524-ASZ

• Number Of Converters: 1
• Package / Case: 24-SSOP
• Number Of Bits: 24
• Data Interface: Serial
• Power Dissipation (max): 14.8mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 4
• Architecture: Delta-Sigma
• Conversion Rate: 617 SPs
• Resolution: 24 bit
• Input Type: Voltage
• Interface Type: Serial (3-Wire)
• Voltage Reference: 2.5 V
• Supply Voltage (max): 5 V
• Supply Voltage (min): 25 mV
• Maximum Power Dissipation: 500 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 25 mV to 5 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1012 - EVAL BOARD FOR CS5524 ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1106-5

mentation amplifier, typically 100 pA, is low
enough to permit large external resistors to divide
down a large external signal without significant
loading. Figure 7 illustrates an example circuit. Re-
fer to
high-voltage (>5 V) measurement.
2.1.5 Voltage Reference
The CS5521/22/23/24/28 devices are specified for
operation with a 2.5 V reference voltage between
the VREF+ and VREF- pins of the device. For a
single-ended reference voltage, such as the
LT1019-2.5, the reference voltage is input into the
VREF+ pin of the converter and the VREF- pin is
grounded.
The differential voltage between the VREF+ and
VREF- can be any voltage from 1.0 V up to VA+,
however, the VREF+ cannot go above VA+ and the
VREF- pin can not go below NBV.
16
±10V
chop clock = 256 Hz
1 MΩ
Voltage
+5 V
Divider
PGIA set for
+ 100 mV
Application Note 158
Figure 7. Input Ranges Greater than 5 V
2.5 V
10 KΩ
BAT85
V ≈ -2.1 V
0.1 µF
NBV
VREF+
VREF-
+
PGIA
-
VA+
+
1N4148
10 µF
10 Ω
Charge Pump
Regulator
∆Σ ADC
CPD
for more details on
1N4148
0.033 µF
VD+
DGND
Charge Pump
Circuitry
0.1 µF
Figure 8 illustrates the input models for the VREF
pins. The dynamic input current for each of the pins
can be determined from the models shown.
2.2 Overview of ADC Register Structure
and Operating Modes
The CS5521/22/23/24/28 ADCs have an on-chip
controller, which includes a number of user-acces-
sible registers. The registers are used to hold offset
and gain calibration results, configure the chip's
operating modes, hold conversion instructions, and
to store conversion data words. Figure 9 depicts a
block diagram of the on-chip controller’s internal
registers for the CS5523/24.
Each of the converters has 24-bit registers to func-
tion as offset and gain calibration registers for each
channel. The converters with two channels have
two offset and two gain calibration registers, the
converters with four channels have four offset and
four gain calibration registers, and the eight chan-
nel converter has eight offset and eight gain cali-
bration registers. These registers hold calibration
results. The contents of these registers can be read
or written by the user. This allows calibration data
to be off-loaded into an external EEPROM. The
user can also manipulate the contents of these reg-
isters to modify the offset or the gain slope of the
converter.
The converters include a 24-bit configuration reg-
ister of which 17 of the bits are used for setting op-
tions such as the conversion mode, operating power
options, setting the chop clock rate of the instru-
Figure 8. Input Model for VREF+ and VREF- Pins
V
i = fV
n
os
V R E F
≤ 25 m V
os
C
f = 3 2.76 8 kH z
CS5521/22/23/24/28
φ C o ars e
2
φ F in e
C = 10 pF
1
DS317F4