CS5524-ASZ Cirrus Logic Inc, CS5524-ASZ Datasheet - Page 25
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CS5524-ASZ
Manufacturer Part Number
CS5524-ASZ
Description
IC ADC 24BIT 4CH 20SSOP
Manufacturer
Cirrus Logic Inc
Specifications of CS5524-ASZ
Number Of Converters
1
Package / Case
24-SSOP
Number Of Bits
24
Data Interface
Serial
Power Dissipation (max)
14.8mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Number Of Adc Inputs
4
Architecture
Delta-Sigma
Conversion Rate
617 SPs
Resolution
24 bit
Input Type
Voltage
Interface Type
Serial (3-Wire)
Voltage Reference
2.5 V
Supply Voltage (max)
5 V
Supply Voltage (min)
25 mV
Maximum Power Dissipation
500 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Input Voltage
25 mV to 5 V
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1012 - EVAL BOARD FOR CS5524 ADC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1106-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS5524-ASZ
Manufacturer:
CIRRUS
Quantity:
20 000
2.2.5 Serial Port Interface
The CS5521/22/23/24/28’s serial interface consists
of four control lines: CS, SCLK, SDI, SDO.
Figure 10 illustrates the serial sequence necessary
to write to, or read from the serial port’s registers.
CS (Chip Select) is the control line which enables
access to the serial port. If the CS pin is tied low,
the port can function as a three-wire interface.
SDI (Serial Data In) is the data signal used to trans-
fer data to the converters.
SDO (Serial Data Out) is the data signal used to
transfer output data from the converters. The SDO
DS317F4
SCLK
SDO
* td = XIN/OWR clock cycles for each conversion except the
SDI
SCLK
SCLK
first conversion which will take XIN/OWR + 7 clock cycles
SDO
SDI
SDI
CS
CS
Command Time
8 SCLKs
Figure 10. Command and Data Word Timing
Command Time
Command Time
8 SCLKs
8 SCLKs
t *
d
8 SCLKs Clear SDO Flag
Write Cycle
MSB
MSB
Read Cycle
output will be held at high impedance any time CS
is at logic 1.
SCLK (Serial Clock) is the serial bit clock which
controls the shifting of data to or from the ADC’s
serial port. The CS pin must be held low (logic 0)
before SCLK transitions can be recognized by the
port logic. To accommodate opto-isolators SCLK
is designed with a Schmitt-trigger input to allow an
opto-isolator with slower rise and fall times to di-
rectly drive the pin. Additionally, SDO is capable
of sinking or sourcing up to 5 mA to directly drive
an opto-isolator LED. SDO will have less than a
400 mV loss in the drive voltage when sinking or
sourcing 5 mA.
Data Time 24 SCLKs
Data Time 24 SCLKs
MSB
Data Time
24 SCLKs
CS5521/22/23/24/28
Clock Cycles
XIN/OWR
LSB
LSB
LSB
25