CS5531-ASZ Cirrus Logic Inc, CS5531-ASZ Datasheet - Page 38

• Manufacturer Part Number: CS5531-ASZ
• Description: IC ADC 16BIT 2CH W/LNA 20SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5531-ASZ

• Number Of Converters: 1
• Package / Case: 20-SSOP
• Number Of Bits: 16
• Sampling Rate (per Second): 3.84k
• Data Interface: Serial
• Power Dissipation (max): 45mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 4
• Architecture: Delta-Sigma
• Conversion Rate: 6.25 SPs to 3840 SPs
• Resolution: 16 bit
• Input Type: Voltage
• Interface Type: Serial (3-Wire)
• Voltage Reference: 2.5 V
• Maximum Power Dissipation: 500 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1111-5

2.9. Digital Filter
The CS5531/32/33/34 have linear phase digital fil-
ters which are programmed to achieve a range of
output word rates (OWRs) as stated in the Channel-
Setup Register Descriptions section. The ADCs use
a Sinc
Sps and 3840 Sps (MCLK = 4.9152 MHz). Other
output word rates are achieved by using the Sinc
filter followed by a Sinc
ble decimation rate. Figure 16 shows the magnitude
response of the 60 Sps filter, while Figures 17 and
18 show the magnitude and phase response of the
filter at 120 Sps. The Sinc
word rates except for the 3200 Sps and 3840 Sps
38
Figure 17. 120 Sps Filter Magnitude Plot to 120 Hz
Figure 16. Digital Filter Response (WR = 60 Sps)
-120
-40
-80
5
0
-120
-40
-80
0
digital filter to output word rates at 3200
0
0
Frequency
60
10
12
14
16
19
32
2
4
6
8
Flatness
-0.01
-0.05
-0.11
-0.19
-0.30
-0.43
-0.59
-0.77
-1.09
-3.13
dB
Frequency (Hz)
120
Frequency (Hz)
40
3
filter with a programma-
3
is active for all output
180
80
240
300
120
5
(MCLK = 4.9152 MHz) rate. The Z-transforms of
the two filters are shown in Figure 19. For the Sinc
filter, “D” is the programmable decimation ratio,
which is equal to 3840/OWR when FRS = 0 and
3200/OWR when FRS = 1.
The converter’s digital filters scale with MCLK.
For example, with an output word rate of 120 Sps,
the filter’s corner frequency is at 31 Hz. If MCLK
is increased to 5.0 MHz, the OWR increases by
1.0175% and the filter’s corner frequency moves to
31.54 Hz. Note that the converter is not specified to
run at MCLK clock frequencies greater than
5 MHz.
Note:
Sinc
Sinc
Figure 18. 120 Sps Filter Phase Plot to 120 Hz
Figure 19. Z-Transforms of Digital Filters
5
3
-180
=
=
180
-90
90
(
------------------------- -
(
(
------------------------ -
(
0
1 z
1 z
1 z
1 z
See the text regarding the Sinc
decimation ratio “D”.
–
–
–
–
0
–
–
–
1 –
80
16
D
)
)
)
)
3
3
5
5
×
(
------------------------- -
CS5531/32/33/34-AS
30
(
1 z
1 z
–
Frequency (Hz)
–
–
4 –
16
)
)
3
3
60
×
(
-----------------------
(
1 z
1 z
–
–
4 –
2 –
)
)
2
2
90
×
(
-----------------------
(
3
1 z
1 z
filter’s
–
–
DS289F5
2 –
1 –
120
)
)
3
3
3