KAD5512P-50Q72 Intersil, KAD5512P-50Q72 Datasheet - Page 20

• Manufacturer Part Number: KAD5512P-50Q72
• Description: IC ADC 12BIT 500MSPS SGL 72-QFN
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KAD5512P-50Q72

• Number Of Bits: 12
• Sampling Rate (per Second): 500M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 460mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 72-VFQFN Exposed Pad
• For Use With: KDC5512EVAL - DAUGHTER CARD FOR KAD5512KDC5512-50EVAL - DAUGHTER CARD FOR KAD5512
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The
SPI bus consists of chip select (CSB), serial clock (SCLK)
serial data output (SDO), and serial data input/output (SDIO).
The maximum SCLK rate is equal to the ADC sample rate
(f
divided by 132 for reads. At f
SCLK is 15.63MHz for writing and 3.79MHz for read
operations. There is no minimum SCLK rate.
The following sections describe various registers that are
used to configure the SPI or adjust performance or functional
parameters. Many registers in the available address space
(0x00 to 0xFF) are not defined in this document. Additionally,
within a defined register there may be certain bits or bit
combinations that are reserved. Undefined registers and
undefined values within defined registers are reserved and
should not be selected. Setting any reserved register or value
may produce indeterminate results.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the
data transfer. By default, all data is presented on the serial
data input/output (SDIO) pin in three-wire mode. The state of
the SDIO pin is set automatically in the communication
protocol (described in the following). A dedicated serial data
output pin (SDO) can be activated by setting 0x00[7] high to
allow operation in four-wire mode.
The SPI port operates in a half duplex master/slave
configuration, with the KAD5512P-50 functioning as a slave.
Multiple slave devices can interface to a single master in
three-wire mode only, since the SDO output of an
unaddressed device is asserted in four wire mode.
SAMPLE
SCLK
SDIO
SCLK
SDIO
CSB
CSB
) divided by 32 for write operations and f
INSTRUCTION/ADDRESS
INSTRUCTION/ADDRESS
SAMPLE
20
= 250MHz, maximum
SAMPLE
FIGURE 37. N-BYTE TRANSFER
FIGURE 36. 2-BYTE TRANSFER
KAD5512P-50
CSB STALLING
DATA WORD 1
CSB STALLING
LAST LEGAL
DATA WORD 1
The chip-select bar (CSB) pin determines when a slave
device is being addressed. Multiple slave devices can be
written to concurrently, but only one slave device can be
read from at a given time (again, only in three-wire mode). If
multiple slave devices are selected for reading at the same
time, the results will be indeterminate.
The communication protocol begins with an
instruction/address phase. The first rising SCLK edge
following a high to low transition on CSB determines the
beginning of the two-byte instruction/address command;
SCLK must be static low before the CSB transition. Data can
be presented in MSB-first order or LSB-first order. The
default is MSB-first, but this can be changed by setting
0x00[6] high. Figures 32 and 33 show the appropriate bit
ordering for the MSB-first and LSB-first modes, respectively.
In MSB-first mode the address is incremented for multi-byte
transfers, while in LSB-first mode it’s decremented.
In the default mode the MSB is R/W, which determines if the
data is to be read (active high) or written. The next two bits,
W1 and W0, determine the number of data bytes to be read
or written (see Table 6). The lower 13 bits contain the first
address for the data transfer. This relationship is illustrated in
Figure 34, and timing values are given in “Switching
Specifications” on page 7.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read from
the ADC (based on the R/W bit status). The data transfer will
continue as long as CSB remains low and SCLK is active.
Stalling of the CSB pin is allowed at any byte boundary
(instruction/address or data) if the number of bytes being
transferred is three or less. For transfers of four bytes or
more, CSB is allowed stall in the middle of the
instruction/address bytes or before the first data byte. If CSB
DATA WORD N
DATA WORD 2
October 9, 2009
FN6805.3