KAD5512P-50Q72 Intersil, KAD5512P-50Q72 Datasheet - Page 22

• Manufacturer Part Number: KAD5512P-50Q72
• Description: IC ADC 12BIT 500MSPS SGL 72-QFN
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KAD5512P-50Q72

• Number Of Bits: 12
• Sampling Rate (per Second): 500M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 460mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 72-VFQFN Exposed Pad
• For Use With: KDC5512EVAL - DAUGHTER CARD FOR KAD5512KDC5512-50EVAL - DAUGHTER CARD FOR KAD5512
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented
value back to the same register.
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By
default, the tri-level NAPSLP pin can select normal
operation, nap or sleep modes (refer to“Nap/Sleep” on
page 17). This functionality can be overridden and controlled
through the SPI. This is an indexed function when controlled
from the SPI, but a global function when driven from the pin.
This register is not changed by a Soft Reset.
Global Device Configuration/Control
ADDRESS 0X70: SKEW_DIFF
The value in the skew_diff register adjusts the timing skew
between the two ADCs cores. The nominal range and
resolution of this adjustment are given in Table 11. The
default value of this register after power-up is 80h.
+Full Scale (0xFF)
Nominal Step Size
–Full Scale (0x00)
Mid–Scale (0x80)
PARAMETER
TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS
0x22[3:0]
–Full Scale (0x00)
TABLE 11. DIFFERENTIAL SKEW ADJUSTMENT
Steps
Bit3
Bit2
Bit1
Bit0
PARAMETER
TABLE 8. COARSE GAIN ADJUSTMENT
VALUE
TABLE 10. POWER-DOWN CONTROL
Steps
000
001
010
100
MEDIUM GAIN
NOMINAL COARSE GAIN ADJUST
0x23[7:0]
0.016%
0.00%
+2%
-2%
256
22
POWER DOWN MODE
DIFFERENTIAL SKEW
Normal Operation
+2.8
+1.4
-2.8
-1.4
(%)
Sleep Mode
Pin Control
Nap Mode
0x25[2:0]
0x70[7:0]
-6.5ps
256
FINE GAIN
0x24[7:0]
0.0016%
-0.20%
0.00%
+0.2%
256
KAD5512P-50
ADDRESS 0X71: PHASE_SLIP
When using the clock divider, it’s not possible to determine
the synchronization of the incoming and divided clock
phases. This is particularly important when multiple ADCs
are used in a time-interleaved system. The phase slip
feature allows the rising edge of the divided clock to be
advanced by one input clock cycle when in CLK/2 mode, as
shown in Figure 38. Execution of a phase_slip command is
accomplished by first writing a ‘0’ to bit 0 at address 71h
followed by writing a ‘1’ to bit 0 at address 71h (32 sclk
cycles).
ADDRESS 0X72: CLOCK_DIVIDE
The KAD5512P-50 has a selectable clock divider that can be
set to divide by two or one (no division). By default, the
tri-level CLKDIV pin selects the divisor (refer to “Clock Input”
on page 16). This functionality can be overridden and
controlled through the SPI, as shown in Table 12. This
register is not changed by a Soft Reset.
ADC0 CLOCK
ADC1 CLOCK
ADC0 CLOCK
ADC1 CLOCK
ADC0 CLOCK
ADC1 CLOCK
FIGURE 38. PHASE SLIP: CLK÷2 MODE, f
SLIP TWICE
SLIP TWICE
SLIP ONCE
SLIP ONCE
CLK
+Full Scale (0xFF)
Nominal Step Size
TABLE 11. DIFFERENTIAL SKEW ADJUSTMENT
CLK
Mid–Scale (0x80)
PARAMETER
ℜ÷
TABLE 12. CLOCK DIVIDER SELECTION
VALUE
000
CLK = CLKP - CLKN
2.00ns
1.00ns
DIFFERENTIAL SKEW
CLOCK DIVIDER
4.00ns
Pin Control
0x70[7:0]
0x72[2:0]
CLOCK
+6.5ps
0.0ps
51fs
= 1000MHz
October 9, 2009
FN6805.3