MAX1167BEEE+ Maxim Integrated Products, MAX1167BEEE+ Datasheet - Page 18

• Manufacturer Part Number: MAX1167BEEE+
• Description: IC ADC 16BIT 200KSPS 16-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1167BEEE+

• Number Of Bits: 16
• Sampling Rate (per Second): 200k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 667mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX1168 external clock 16-bit-wide data-transfer
mode requires 32 SCLK cycles for completion (Figure 11).
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified mini-
mum time (t
conversion immediately aborts the conversion and
places the MAX1168 in shutdown.
Force DSPR high and DSEL low (MAX1168) for the SPI/
QSPI/MICROWIRE interface mode. The falling edge of
CS wakes the analog circuitry and allows SCLK to clock
in data (Figure 12). DOUT changes from high-Z to logic
low after CS is brought low. Input data latches on the ris-
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Figure 11. SPI External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)
Figure 12. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing
18
INTERNAL
STATE
STATE
DOUT
SCLK
DOUT
SCLK
______________________________________________________________________________________
ADC
ADC
EOC
DIN
CLK
DIN
CS
CS
DSPR
DSEL
Internal Clock 8-Bit-Wide Data-Transfer and
X = DON
MSB
X = DON
DSPR = DV
MSB
1
CSW
1
,
T CARE
,
T CARE
Scan Mode (MAX1167 and MAX1168)
). Forcing CS high in the middle of a
DD
, DSEL = GND (MAX1168 ONLY)
LSB
1
8
LSB
0
8
t
ACQ
X
2
X
t
ACQ
X
X
6
X
X
X
t
CONV
X
16
MSB
ing edge of SCLK. The command/configuration/control
register begins reading DIN on the first SCLK rising edge
and ends on the rising edge of the 8th SCLK cycle. The
MAX1167/MAX1168 select the proper channel for con-
version on the rising edge of the 3rd SCLK cycle. The
internal oscillator activates 125ns after the rising edge of
the 8th SCLK cycle. Turn off the external clock while the
internal clock is on. Turning off SCLK ensures the lowest
noise performance during acquisition. Acquisition begins
on the 2nd rising edge of the internal clock and ends on
the falling edge of the 6th internal clock cycle. Each bit
of the conversion result shifts into memory as it becomes
available. The conversion result is available (MSB first) at
DOUT on the falling edge of EOC. The internal oscillator
and analog circuitry are shut down on the high-to-low
EOC transition. Use the EOC high-to-low transition as the
25
IDLE
MSB
9
POWER-DOWN
t
CONV
24
16
LSB
32
LSB
24
IDLE
X