AD7194BCPZ Analog Devices Inc, AD7194BCPZ Datasheet - Page 42

• Manufacturer Part Number: AD7194BCPZ
• Description: IC ADC 24BIT SPI 4.8K 32-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD7194BCPZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 24
• Sampling Rate (per Second): 4.8k
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN, CSP Exposed Pad
• Resolution (bits): 24bit
• Input Channel Type: Pseudo Differential
• Supply Voltage Range - Analogue: 3V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Supply: RoHS Compliant
• Sampling Rate: 4.8kSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AD7194BRUZ; AD7194BRUZ

AD7194
The output data rate equals
where:
f
f
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
When the analog input is constant or a channel change occurs,
valid conversions are available at a constant output data rate.
When conversions are being performed on a single channel and
a step change occurs on the analog input, the ADC continues to
output fully settled conversions if the step change is synchronized
with the conversion process. If the step change is asynchronous,
one conversion is output from the ADC that is not completely
settled (see Figure 38).
Table 31 provides examples of output data rates and the corres-
ponding FS values.
Table 31. Examples of Output Data Rates and the
Corresponding Settling Time (Zero Latency)
FS[9:0]
480
96
80
ADC
CLK
is the master clock (4.92 MHz nominal).
is the output data rate.
f
ADC
ANALOG
OUTPUT
INPUT
ADC
= 1/t
Output Data Rate (Hz)
3.3
16.7
20
SETTLE
Figure 38. Sinc
= f
CLK
/(3 × 1024 × FS[9:0])
3
Zero Latency Operation
1/
f
ADC
Settling Time (ms)
300
60
50
SETTLED
FULLY
Rev. 0 | Page 42 of 56
Sinc
Figure 39 show the frequency response of the sinc
FS[9:0] is set to 96 and the master clock equals 4.92 MHz. The
output data rate is equal to 50 Hz when zero latency is disabled
and 16.7 Hz when zero latency is enabled. The sinc
50 Hz ± 1 Hz rejection of 95 dB minimum for a stable master clock.
When FS[9:0] is set to 80 and the master clock equals
4.92 MHz, 60 Hz rejection is achieved (see Figure 40). The
output data rate is equal to 60 Hz when zero latency is disabled
and 20 Hz when zero latency is enabled. The sinc
rejection of 95 dB minimum at 60 Hz ± 1 Hz, assuming a stable
master clock.
3
–100
–120
–100
–110
–120
–110
50 Hz/60 Hz Rejection
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
0
0
Figure 39. Sinc
Figure 40. Sinc
25
30
50
3
3
Filter Response (FS[9:0] = 96)
Filter Response (FS[9:0] = 80)
FREQUENCY (Hz)
FREQUENCY (Hz)
60
75
90
100
120
125
3
3
filter has
3
filter when
filter gives
150
150