MAX19516ETM+ Maxim Integrated Products, MAX19516ETM+ Datasheet
MAX19516ETM+
Specifications of MAX19516ETM+
Related parts for MAX19516ETM+
MAX19516ETM+ Summary of contents
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... Reversible Bit Order (Programmable) o Data Output Test Patterns o Small 7mm x 7mm 48-Pin Thin QFN Package with Exposed Pad PART MAX19516ETM+ + Denotes a lead(Pb)-free/RoHS-compliant package Exposed pad. Pin Configuration appears at end of data sheet. SPI is a trademark of Motorola, Inc. Features Ordering Information ...
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Dual-Channel, 10-Bit, 100Msps ADC ABSOLUTE MAXIMUM RATINGS OVDD, AVDD to GND............................................-0.3V to +3.6V CMA, CMB, REFIO, INA+, INA-, INB+, INB- to GND ......................................................-0.3V to +2.1V CLK+, CLK-, SYNC, SPEN, CS, SCLK, SDIN to GND ..........-0.3V to the lower of (V ...
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Dual-Channel, 10-Bit, 100Msps ADC ELECTRICAL CHARACTERISTICS (continued 1.8V, internal reference, differential clock, V AVDD OVDD tion = 50Ω -40°C to +85°C, unless otherwise noted. Typical values are PARAMETER SYMBOL DYNAMIC PERFORMANCE ...
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Dual-Channel, 10-Bit, 100Msps ADC ELECTRICAL CHARACTERISTICS (continued 1.8V, internal reference, differential clock, V AVDD OVDD tion = 50Ω -40°C to +85°C, unless otherwise noted. Typical values are PARAMETER SYMBOL INTERCHANNEL CHARACTERISTICS ...
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Dual-Channel, 10-Bit, 100Msps ADC ELECTRICAL CHARACTERISTICS (continued 1.8V, internal reference, differential clock, V AVDD OVDD tion = 50Ω -40°C to +85°C, unless otherwise noted. Typical values are PARAMETER SYMBOL CLOCK INPUT ...
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Dual-Channel, 10-Bit, 100Msps ADC ELECTRICAL CHARACTERISTICS (continued 1.8V, internal reference, differential clock, V AVDD OVDD tion = 50Ω -40°C to +85°C, unless otherwise noted. Typical values are PARAMETER SYMBOL POWER-MANAGEMENT CHARACTERISTICS ...
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Dual-Channel, 10-Bit, 100Msps ADC ELECTRICAL CHARACTERISTICS (continued 1.8V, internal reference, differential clock, V AVDD OVDD tion = 50Ω -40°C to +85°C, unless otherwise noted. Typical values are PARAMETER SYMBOL POWER REQUIREMENTS ...
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Dual-Channel, 10-Bit, 100Msps ADC ( 1.8V, internal reference, differential clock, V AVDD OVDD tion = 50Ω +25°C, unless otherwise noted.) A 3MHz INPUT FFT PLOT 2.99911499MHz -0.446dBFS IN -20 ...
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Dual-Channel, 10-Bit, 100Msps ADC ( 1.8V, internal reference, differential clock, V AVDD OVDD tion = 50Ω +25°C, unless otherwise noted.) A SINGLE-ENDED PERFORMANCE vs. INPUT FREQUENCY 85 SFDR2 80 SFDR1 75 70 SNR -THD 65 ...
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Dual-Channel, 10-Bit, 100Msps ADC ( 1.8V, internal reference, differential clock, V AVDD OVDD tion = 50Ω +25°C, unless otherwise noted.) A ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE 67.5 67.0 66.5 66.0 65.5 65.0 64.5 64.0 ...
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Dual-Channel, 10-Bit, 100Msps ADC ( 1.8V, internal reference, differential clock, V AVDD OVDD tion = 50Ω +25°C, unless otherwise noted.) A OFFSET ERROR vs. TEMPERATURE 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 ...
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Dual-Channel, 10-Bit, 100Msps ADC PIN NAME 1, 12, 13, 48 AVDD Analog Supply Voltage. Bypass each AVDD input pair (1, 48) and (12, 13) to GND with 0.1µF. 2 CMA Channel A Common-Mode Input-Voltage Reference 3 INA+ Channel A Positive ...
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Dual-Channel, 10-Bit, 100Msps ADC PIN NAME 40 D7A Channel A Three-State Digital Output, Bit 7 41 D8A Channel A Three-State Digital Output, Bit 8 42 D9A Channel A Three-State Digital Output, Bit 9 (MSB) 43 DORA Channel A Data Over ...
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Dual-Channel, 10-Bit, 100Msps ADC INA+ T/H INA- CMA REFIO CMB INB+ T/H INB- CLK+ CLK- SYNC CS SERIAL PORT SCLK SDIN CONTROL REGISTERS SPEN Figure 2. Functional Diagram CMA INA+ 2kΩ 2kΩ INA- SAMPLING CLOCK *V PROGRAMMABLE FROM 0.45V TO ...
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Dual-Channel, 10-Bit, 100Msps ADC INTERNAL GAIN—BYPASS REFIO EXTERNAL GAIN CONTROL—DRIVE REFIO REFIO 1.250V 10kΩ BANDGAP SCALE AND BUFFER REFERENCE LEVEL SHIFT Figure 4. Simplified Reference Schematic Table 1. Parallel-Interface Pin Functionality SPEN SDIN/FORMAT 0 SDIN AVDD 1 ...
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Dual-Channel, 10-Bit, 100Msps ADC CS SCLK SDIN R R WRITE 1 = READ Figure 6. Serial-Interface Communication Cycle t CSS CS SCLK t t SDS SDH SDIN WRITE Figure 7. Serial-Interface Timing Diagram Serial Programming ...
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Dual-Channel, 10-Bit, 100Msps ADC Register address 0Ah is a special-function register. Writing data 5Ah to register 0Ah initiates a register reset. When this operation is executed, all control regis- Table 2. Register 0Ah Status Byte BIT NO. VALUE 7 0 ...
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Dual-Channel, 10-Bit, 100Msps ADC In addition to power management, the HPS_SHDN1 and HPS_SHDN0 activate an A+B adder mode. In this mode, the results from both channels are averaged. Control Bits: HPS_SHDN0 STBY_SHDN0 HPS_SHDN1 STBY_SHDN1 ...
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Dual-Channel, 10-Bit, 100Msps ADC Digital Output Power Management (02h) BIT 7 BIT Bit 7–4 Don’t care Bit 3, 2 PD_DOUT_1, PD_DOUT_0: Power-down digital output state control 00 = Digital output three state (default Digital output ...
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Dual-Channel, 10-Bit, 100Msps ADC Data/DCLK Timing (03h) BIT 7 BIT 6 BIT 5 DA_BYPASS DLY_HALF_T DCLKTIME_2 Bit 7 DA_BYPASS: Data aligner bypass 0 = Nominal 1 = Bypasses data aligner delay line to minimize output data latency with respect to ...
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Dual-Channel, 10-Bit, 100Msps ADC CHA Data Output Termination Control (04h) BIT 7 BIT 6 BIT CT_DCLK_2_A Bit 7, 6 Don’t care Bit CT_DCLK_2_A, CT_DCLK_1_A, CT_DCLK_0_A: CHA DCLK termination control 000 = 50Ω (default) 001 ...
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Dual-Channel, 10-Bit, 100Msps ADC Clock Divide/Data Format/Test Pattern (06h) BIT 7 BIT 6 TEST_PATTERN TEST_DATA FORMAT_1 Bit 7 TEST_PATTERN: Test pattern selection 0 = Ramps from 0 to 1023 (offset binary) and repeats (subsequent formatting applied) (default Data ...
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Dual-Channel, 10-Bit, 100Msps ADC Common Mode (08h) BIT 7 BIT 6 CMI_SELF_B CMI_ADJ_2_B CMI_ADJ_1_B CMI_ADJ_0_B Bit 7 CMI_SELF_B: CHB connect input common-mode to analog inputs 0 = Internal common-mode voltage is NOT applied to inputs (default Internal common-mode ...
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Dual-Channel, 10-Bit, 100Msps ADC 100Ω TERMINATION (PROGRAMMABLE) CLK+ AVDD 5kΩ 50Ω 10kΩ 20kΩ 50Ω THRESHOLD 5kΩ GND CLK- SELF-BIAS TURNED OFF FOR SINGLE-ENDED CLOCK OR POWER-DOWN. Figure 8. Simplified Clock Input Schematic SAMPLING INSTANT t AD IN_ SAMPLE ON RISING ...
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Dual-Channel, 10-Bit, 100Msps ADC SAMPLING INSTANT IN_ SAMPLE ON RISING EDGE n SAMPLE CLOCK t DD CHB DATA, DOR n-10 DCLK SAMPLE CLOCK IS THE DERIVED CLOCK FROM (CLK+ - CLK-)/CLOCK DIVIDER, IN_ = IN_+ - IN_-. MUX_CH (BIT 2, ...
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Dual-Channel, 10-Bit, 100Msps ADC SUV SYNC INPUT CLK (0) (1) 1x DIVIDED CLK (STATE) (1) ( SUV SYNC INPUT CLK (0) (1) (2) (1) (2) (3) 1x DIVIDED ...
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Dual-Channel, 10-Bit, 100Msps ADC SUV SYNC INPUT CLK (0) (1) 1x DIVIDED CLK (STATE) (1) ( SUV SYNC INPUT CLK (0) (1) (2) (1) (2) (3) 1x DIVIDED ...
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Dual-Channel, 10-Bit, 100Msps ADC Table 4. Data Timing Controls DATA TIMING CONTROL Data aligner bypass. When this control is active (high), data and DCLK delay is reduced by DA_BYPASS approximately 3.4ns (relative to DA_BYPASS = 0). When this control is ...
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Dual-Channel, 10-Bit, 100Msps ADC FACTORY-DEFAULT NOMINAL DATA TIMING vs. SAMPLING RATE 2 1.8V OVDD DA_BYPASS = 1 1.5 1.0 0 SAMPLING RATE (Msps) Figure 13. Default Data Timing (V OVDD FACTORY-DEFAULT NOMINAL DATA ...
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Dual-Channel, 10-Bit, 100Msps ADC Table 7. Recommended Timing Adjustments (V SAMPLING RATE (Msps) FROM TO DA_BYPASS 100 Table 8. Allowed Settings of DCLKTIME and DTIME for DA_BYPASS = 1 DTIME<2:0> 111 (-3T/16) 111 (-3T/16) 110 ...
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Dual-Channel, 10-Bit, 100Msps ADC AVDD (PINS 1, 12, 13, 48) REFERENCE GND Figure 17. Integrated Voltage Regulator 36.5Ω 0.1µF 0. N.C. N.C. 0.1µ 36.5Ω MINI-CIRCUITS 0.5% ADT1-1WT Figure 18. Transformer-Coupled Input ...
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Dual-Channel, 10-Bit, 100Msps ADC V IN 0.1µF MAX4108 100Ω 0.1µF 100Ω 0.1µF Figure 20. Single-Ended, AC-Coupled Input Drive The circuit of Figure 19 also converts a single-ended input signal to a fully differential signal. Figure 19 uti- lizes an additional ...
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Dual-Channel, 10-Bit, 100Msps ADC Small-Signal Noise Floor (SSNF) SSNF is the integrated noise and distortion power in the Nyquist band for small-signal inputs. The DC offset is excluded from this noise calculation. For this converter, a small signal is defined ...
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Dual-Channel, 10-Bit, 100Msps ADC TOP VIEW D4A D5A D6A D7A D8A D9A DORA DCLKA SDIN/FORMAT SCLK/DIV CS/OUTSEL AVDD For the latest package outline information and land patterns www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 35 © 2010 Maxim Integrated Products DESCRIPTION Maxim is a registered trademark of Maxim Integrated Products, Inc ...