MAX19516ETM+ Maxim Integrated Products, MAX19516ETM+ Datasheet - Page 30

• Manufacturer Part Number: MAX19516ETM+
• Description: IC ADC 10BIT 100MSPS DUAL 48TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19516ETM+

• Number Of Bits: 10
• Sampling Rate (per Second): 100M
• Data Interface: Serial, Parallel
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Conversion Rate: 100 MSPs
• Resolution: 10 bit
• Interface Type: SPI
• Snr: 60.1 dB
• Voltage Reference: 1.25 V
• Supply Voltage (max): 3.5 V
• Supply Voltage (min): 1.7 V
• Maximum Power Dissipation: 3200 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 1.8 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual-Channel, 10-Bit, 100Msps ADC
Table 7. Recommended Timing Adjustments (V
Table 8. Allowed Settings of DCLKTIME and DTIME for DA_BYPASS = 1
The MAX19516 includes an integrated self-sensing lin-
ear voltage regulator on the analog supply (AVDD). See
Figure 17. When the applied voltage on AVDD is below
2V, the voltage regulator is bypassed, and the core
analog circuitry operates from the externally applied
voltage. If the applied voltage on AVDD is higher than
2V, the regulator bypass switches off, and voltage reg-
ulator mode is enabled. When in voltage regulation
mode, the internal-core analog circuitry operates from a
stable 1.8V supply voltage provided by the regulator.
The regulator provides an output voltage of 1.8V over a
2.3V to 3.5V AVDD input-voltage range. Since the
power-supply current is constant over this voltage
range, analog power dissipation is proportional to the
applied voltage.
30
111 (-3T/16)
110 (-2T/16)
101 (-1T/16)
000 (nominal)
001 (+1T/16)
010 (+2T/16)
011 (+3T/16)
Power-On Reset
Software Reset
Hardware Reset A register reset is initiated by the falling edge on the SHDN pin when SPEN is high.
RESET MODE
SAMPLING RATE (Msps)
DTIME<2:0>
Table 9. Reset Methods
FROM
______________________________________________________________________________________
50
73
88
Upon power-up (AVDD supply voltage and clock signal applied), the POR (power-on-reset) circuit initiates a
register reset.
Write data 5Ah to address 0Ah to initiate register reset.
Integrated Voltage Regulator
111 (-3T/16)
110 (-2T/16); 111 (-3T/16)
101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
001 (+1T/16); 000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
010 (+2T/16); 001 (+1T/16); 000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
011 (+3T/16); 010 (+2T/16); 001 (+1T/16); 000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
100
TO
73
88
DA_BYPASS
1
1
1
ALLOWED DCLKTIME<2:0> SETTINGS
DLY_HALF_T
DESCRIPTION
The user-programmable register default settings and
other factory-programmed settings are stored in non-
volatile memory. Upon device power-up, these values
are loaded into the control registers. This operation
occurs after application of supply voltage to AVDD and
application of an input clock signal. The register values
are retained as long as AVDD is applied. While AVDD is
applied, the registers can be reset, which will overwrite
all user-programmed registers with the default values.
This reset operation can be initiated by software com-
mand through the serial-port interface or by hardware
control using the SPEN and SHDN inputs. The reset
time is proportional to the ADC clock period and
requires 85µs at 100Msps. Table 9 summarizes the
reset methods.
0
0
0
OVDD
V
OVDD
= 3.3V)
= 3.3V
DTIME<2:0>
000
101
110
Power-On and Reset
DCLKTIME<2:0>
000
101
110