LTC2402CMS Linear Technology, LTC2402CMS Datasheet - Page 14

• Manufacturer Part Number: LTC2402CMS
• Description: IC ADC 24BIT 2CH MICROPWR 10MSOP
• Manufacturer: Linear Technology

Specifications of LTC2402CMS

• Number Of Bits: 24
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC2401/LTC2402
external serial clock. If the change occurs during the
conversion state, the result of the conversion in progress
may be outside specifications but the following conver-
sions will not be affected. If the change occurs during the
data output state and the converter is in the Internal SCK
mode, the serial clock duty cycle may be affected but the
serial data stream will remain valid.
Table 3 summarizes the duration of each state as a
function of F
SERIAL INTERFACE
The LTC2401/LTC2402 transmit the conversion results
and receives the start of conversion command through a
synchronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the
converter status and during the data output state it is used
to read the conversion result.
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 9) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2401/LTC2402 create their own serial
clock by dividing the internal conversion clock by 8. In the
External SCK mode of operation, the SCK pin is used as
Table 3. LTC2401/LTC2402 State Duration
State
CONVERT
SLEEP
DATA OUTPUT
14
O
.
Operating Mode
Internal Oscillator
External Oscillator
Internal Serial Clock
External Serial Clock with
Frequency f
U
U
SCK
kHz
W
F
(60Hz Rejection)
F
(50Hz Rejection)
F
with Frequency f
(f
F
(Internal Oscillator)
F
Frequency f
O
O
O
O
O
EOSC
= LOW
= HIGH
= External Oscillator
= LOW/HIGH
= External Oscillator with
U
/2560 Rejection)
EOSC
EOSC
kHz
kHz
input. The internal or external SCK mode is selected on
power-up and then reselected every time a HIGH-to-LOW
transition is detected at the CS pin. If SCK is HIGH or float-
ing at power-up or during this transition, the converter
enters the internal SCK mode. If SCK is LOW at power-up
or during this transition, the converter enters the external
SCK mode.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 8), drives the serial
data during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.
When CS (Pin 7) is HIGH, the SDO driver is switched to a
high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = 0.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 7), is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.
Duration
133ms
160ms
20510/f
As Long As CS = HIGH Until CS = 0 and SCK
As Long As CS = LOW But Not Longer Than 1.67ms
(32 SCK cycles)
As Long As CS = LOW But Not Longer Than 256/f
(32 SCK cycles)
As Long As CS = LOW But Not Longer Than 32/f
(32 SCK cycles)
EOSC
s
SCK
EOSC
ms
ms