LTC2402CMS Linear Technology, LTC2402CMS Datasheet - Page 19

• Manufacturer Part Number: LTC2402CMS
• Description: IC ADC 24BIT 2CH MICROPWR 10MSOP
• Manufacturer: Linear Technology

Specifications of LTC2402CMS

• Number Of Bits: 24
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is
LOW.
Whenever SCK is LOW, the LTC2401/LTC2402’s internal
pull-up at pin SCK is disabled. Normally, SCK is not
externally driven if the device is in the internal SCK timing
mode. However, certain applications may require an ex-
ternal driver on SCK. If this driver goes Hi-Z after output-
ting a LOW signal, the LTC2401/LTC2402’s internal pull-
up remains disabled. Hence, SCK remains LOW. On the
next falling edge of CS, the device is switched to the
external SCK timing mode. By adding an external 10k pull-
up resistor to SCK, this pin goes HIGH once the external
driver goes Hi-Z. On the next CS falling edge, the device
will remain in the internal SCK timing mode.
(INTERNAL)
SDO
SCK
CS
Hi-Z
SLEEP
> t
EOCtest
BIT 0
EOC
U
CONVERSION
Hi-Z
DATA OUTPUT
TEST EOC
U
Hi-Z
Figure 9. Internal Serial Clock, Reduced Data Output Length
W
TEST EOC
SLEEP
ANALOG INPUT RANGE
(V
Hi-Z
ZS
REF
REFERENCE VOLTAGE
0V TO FS
ZS
SET
<t
FS
= FS
EOCtest
SET
SET
– 0.12V
BIT 31
U
SET
EOC
+ 0.1V TO V
+ 0.12V
SET
– ZS
– 100mV
REF
SET
1 F
2.7V TO 5.5V
REF
CH0/CH1
TO
BIT 30
)
CC
1
2
3
4
5
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0), SCK
will go LOW. Once CS goes HIGH (within the time period
defined above as t
For a heavy capacitive load on the SCK pin, the internal
pull-up may not be adequate to return SCK to a HIGH level
before CS goes low again. This is not a concern under
normal conditions where CS remains LOW after detecting
EOC = 0. This situation is easily overcome by adding an
external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground (Pin 6),
simplifying the user interface or isolation barrier.
V
FS
CH1
ZS
CH0
CC
SET
SET
LTC2402
BIT 29
SIG
SDO
GND
SCK
CS
F
O
DATA OUTPUT
BIT 28
10
9
8
7
6
EXR
EOCtest
BIT 27
MSB
V
CC
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
LTC2401/LTC2402
), the internal pull-up is activated.
BIT 26
BIT 8
CONVERSION
V
Hi-Z
CC
10k
TEST EOC
19
24012 F09