LTC2415-1CGN Linear Technology, LTC2415-1CGN Datasheet - Page 14

• Manufacturer Part Number: LTC2415-1CGN
• Description: IC ADC 24BIT DIFFINPUT/REF16SSOP
• Manufacturer: Linear Technology

Specifications of LTC2415-1CGN

• Number Of Bits: 24
• Sampling Rate (per Second): 13.75
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC2415/LTC2415-1
Output Data Format
The LTC2415/LTC2415-1 serial output data stream is 32
bits long. The first 3 bits represent status information
indicating the sign and conversion state. The next 24 bits
are the conversion result, MSB first. The remaining 5 bits
are sub LSBs beyond the 24-bit level that may be included
in averaging or discarded without loss of resolution. The
third and fourth bit together are also used to indicate an
underrange condition (the differential input voltage is
below –FS) or an overrange condition (the differential
input voltage is above +FS).
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If V
bit is LOW.
Bit 28 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 29 also
provides the underrange or overrange indication. If both
Bit 29 and Bit 28 are HIGH, the differential input voltage is
above +FS. If both Bit 29 and Bit 28 are LOW, the
differential input voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2415/LTC2415-1 Status Bits
Input Range
V
0V V
–0.5 • V
V
Bits 28-5 are the 24-bit conversion result MSB first.
Bit 5 is the least significant bit (LSB).
Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 may
be included in averaging or discarded without loss of
resolution.
14
IN
IN
< – 0.5 • V
0.5 • V
IN
REF
< 0.5 • V
REF
V
REF
IN
REF
< 0V
IN
is >0, this bit is HIGH. If V
U
U
Bit 31 Bit 30 Bit 29 Bit 28
EOC
0
0
0
0
W
DMY
0
0
0
0
IN
SIG
is <0, this
U
1
1
0
0
MSB
1
0
1
0
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the first
rising edge of SCK. Bit 30 is shifted out of the device on the
first falling edge of SCK. The final data bit (Bit 0) is shifted
out on the falling edge of the 31st SCK and may be latched
on the rising edge of the 32nd SCK pulse. On the falling
edge of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the IN
within the – 0.3V to (V
operating range, a conversion result is generated for any
differential input voltage V
+FS = 0.5 • V
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
Offset Accuracy and Drift
Unlike the LTC2410/LTC2413 and the entire LTC2400 fam-
ily, the LTC2415/LTC2415-1 do not perform an offset
calibration every cycle. The reason for this is to increase the
data output rate while maintaining line frequency rejection.
While the initial accuracy of the LTC2415/LTC2415-1
offset is within 2mV (see Figure 4) several unique proper-
ties of the LTC2415/LTC2415-1 architecture nearly elimi-
nate the drift of the offset error with respect to temperature
and supply.
As shown in Figure 5, the offset variation with temperature
is less than 0.6ppm over the complete temperature range
of –50 C to 100 C. This corresponds to a temperature drift
of 0.004ppm/ C.
REF
. For differential input voltages greater than
CC
IN
+ 0.3V) absolute maximum
from –FS = –0.5 • V
+
and IN
–
pins is maintained
sn2415 24151fs
REF
to