LTC2415-1CGN Linear Technology, LTC2415-1CGN Datasheet - Page 20

• Manufacturer Part Number: LTC2415-1CGN
• Description: IC ADC 24BIT DIFFINPUT/REF16SSOP
• Manufacturer: Linear Technology

Specifications of LTC2415-1CGN

• Number Of Bits: 24
• Sampling Rate (per Second): 13.75
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC2415/LTC2415-1
APPLICATIO S I FOR ATIO
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion enters the sleep state. On the
falling edge of EOC, the conversion result is loaded into an
internal static shift register. The device remains in the
sleep state until the first rising edge of SCK. Data is shifted
out the SDO pin on each falling edge of SCK enabling
external circuitry to latch data on the rising edge of SCK.
EOC can be latched on the first rising edge of SCK. On the
32nd falling edge of SCK, SDO goes HIGH (EOC = 1)
indicating a new conversion has begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 11.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
20
(EXTERNAL)
SDO
SCK
CS
SLEEP
U
BIT 0
EOC
CONVERSION
Hi-Z
U
DATA OUTPUT
TEST EOC
Figure 9. External Serial Clock, Reduced Data Output Length
Hi-Z
W
TEST EOC
ANALOG INPUT RANGE
SLEEP
–0.5V
Hi-Z
REF
1, 7, 8, 9, 10, 15, 16
0.1V TO V
REFERENCE
BIT 31
U
TO 0.5V
EOC
VOLTAGE
1 F
2.7V TO 5.5V
REF
CC
BIT 30
2
3
4
5
6
V
REF
REF
IN
IN
GND
CC
LTC2415-1
+
–
LTC2415/
+
–
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the sleep state, CS must be pulled HIGH
before the first rising edge of SCK. In the internal SCK
timing mode, SCK goes HIGH and the device begins
outputting data at time t
(if EOC = 0) or t
during the falling edge of EOC). The value of t
(LTC2415), 26 s (LTC2415-1) if the device is using its
internal oscillator (F
BIT 29
SDO
SCK
SIG
CS
F
O
14
13
12
11
DATA OUTPUT
BIT 28
MSB
3-WIRE
SPI INTERFACE
V
EOCtest
CC
= 50Hz REJECTION (LTC2415)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2415)
= 50Hz/60Hz REJECTION (LTC2415-1)
BIT 27
0
= logic LOW or HIGH). If F
after EOC goes LOW (if CS is LOW
EOCtest
BIT 9
after the falling edge of CS
BIT 8
CONVERSION
Hi-Z
EOCtest
TEST EOC
O
sn2415 24151fs
2415 F09
is driven
is 23 s