LTC1748CFW#TR Linear Technology, LTC1748CFW#TR Datasheet - Page 12

• Manufacturer Part Number: LTC1748CFW#TR
• Description: IC ADC SMPL 14BIT 80MSPS 48TSSOP
• Manufacturer: Linear Technology

Specifications of LTC1748CFW#TR

• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 1.55W
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC1748
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and visa versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input
is held. While ENC is high, the held input voltage is
buffered by the S/H amplifier which drives the first pipelined
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low,
the first stage produces its residue which is acquired by
the second stage. At the same time, the input S/H goes
back to acquiring the analog input. When ENC goes back
high, the second stage produces its residue which is
acquired by the third stage. An identical process is re-
peated for the third stage, resulting in a third stage residue
that is sent to the fourth stage ADC for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC1748
CMOS differential sample-and-hold. The differential ana-
log inputs are sampled directly onto sampling capacitors
(C
capacitor sampling results in lowest possible noise for a
given sampling capacitor size. The capacitors shown
attached to each input (C
all other capacitance associated with each input.
During the sample phase when ENC/ENC is low, the
transmission gate connects the analog inputs to the sam-
pling capacitors and they charge to, and track the differen-
tial input voltage. When ENC/ENC transitions from low to
12
SAMPLE
) through CMOS transmission gates. This direct
U
PARASITIC
U
) are the summation of
W
U
high the sampled input voltage is held on the sampling
capacitors. During the hold phase when ENC/ENC is high
the sampling capacitors are disconnected from the input
and the held voltage is passed to the ADC core for
processing. As ENC/ENC transitions from high to low the
inputs are reconnected to the sampling capacitors to
acquire a new sample. Since the sampling capacitors still
hold the previous sample, a charging glitch proportional to
the change in voltage between samples will be seen at this
time. If the change between the last sample and the new
sample is small the charging glitch seen at the input will be
small. If the input change is large, such as the change seen
with input frequencies near Nyquist, then a larger charging
glitch will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential drive
to achieve specified performance. Each input should swing
a common mode voltage of 2.35V. The V
(Pin 2) may be used to provide the common mode bias level.
V
to set the DC input level or as a reference level to an op amp
differential driver circuit. The V
ground close to the ADC with a 4.7 F or greater capacitor.
0.8V for the 3.2V range or 0.5V for the 2V range, around
CM
A
A
ENC
ENC
IN
IN
can be tied directly to the center tap of a transformer
+
–
LTC1748
V
V
2V
2V
DD
DD
6k
6k
Figure 2. Equivalent Input Circuit
5V
C
4pF
C
4pF
PARASITIC
PARASITIC
CM
BIAS
pin must be bypassed to
CM
C
C
SAMPLE
SAMPLE
output pin
4pF
4pF
1748 F02
1748fa