LTC1748CFW#TR Linear Technology, LTC1748CFW#TR Datasheet - Page 16

• Manufacturer Part Number: LTC1748CFW#TR
• Description: IC ADC SMPL 14BIT 80MSPS 48TSSOP
• Manufacturer: Linear Technology

Specifications of LTC1748CFW#TR

• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 1.55W
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC1748
At sample rates slower than 80Msps the duty cycle can
vary from 50% as long as each half cycle is at least 6ns.
The lower limit of the LTC1748 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating fre-
quency for the LTC1748 is 1Msps.
DIGITAL OUTPUTS
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50 to external
circuitry and may eliminate the need for external damping
resistors.
Output Loading
As with all high speed/high resolution converters the
digital output loading can affect the performance. The
digital outputs of the LTC1748 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF. A resistor in series with the
16
U
U
LATCH
FROM
DATA
OE
W
Figure 9. Equivalent Circuit for a Digital Output Buffer
PREDRIVER
DD
LOGIC
V
DD
and OGND, iso-
U
V
DD
output may be used but is not required since the ADC has
a series resistor of 43 on chip.
Lower OV
from the digital outputs.
Format
The LTC1748 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MSBINV pin; high selects offset binary.
Overflow Bit
An overflow output bit indicates when the converter is
overranged or underranged. When OF outputs a logic high
the converter is either overranged or underranged.
Output Clock
The ADC has a delayed version of the ENC input available
as a digital output, CLKOUT. The CLKOUT pin can be used
to synchronize the converter data to the digital system.
This is necessary when using a sinusoidal encode. Data
will be updated just after CLKOUT falls and can be latched
on the rising edge of CLKOUT.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 3V
supply then OV
OV
DD
LTC1748
DD
43
voltages will also help reduce interference
1748 F09
DD
OV
OGND
should be tied to that same 3V supply.
DD
0.1 F
0.5V TO
V
TYPICAL
DATA
OUTPUT
DD
DD
, should be tied
1748fa