LTC1604ACG#PBF Linear Technology, LTC1604ACG#PBF Datasheet - Page 8

• Manufacturer Part Number: LTC1604ACG#PBF
• Description: IC A/D CONV 16BIT SAMPLNG 36SSOP
• Manufacturer: Linear Technology

Specifications of LTC1604ACG#PBF

• Number Of Bits: 16
• Sampling Rate (per Second): 333k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 350mW
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC1604
APPLICATIONS
8
CONVERSION DETAILS
The LTC1604 uses a successive approximation algorithm
and internal sample-and-hold circuit to convert an analog
signal to a 16-bit parallel output. The ADC is complete with
a sample-and-hold, a precision reference and an internal
clock. The control logic provides easy interface to micro-
processors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) resets. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from the
Most Significant Bit (MSB) to the Least Significant Bit
(LSB). Referring to Figure 1, the A
acquired during the acquire phase and the comparator
offset is nulled by the zeroing switches. In this acquire
phase, a duration of 480ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
During the convert phase the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the C
transferring the differential analog input charge onto the
A
A
IN
IN
+
–
SAMPLE
SAMPLE
+V
Figure 1. Simplified Block Diagram
DAC
HOLD
HOLD
–V
U
DAC
C
C
–C
+C
SMPL
SMPL
DAC
DAC
INFORMATION
U
SMPL
SAR
ZEROING SWITCHES
IN
+
–
capacitors to ground,
W
+
HOLD
HOLD
COMP
16
and A
LATCHES
OUTPUT
IN
–
U
inputs are
•
•
•
1604 F01
D15
D0
summing junctions. This input charge is successively
compared with the binary-weighted charges supplied by
the differential capacitive DAC. Bit decisions are made by
the high speed comparator. At the end of a conversion, the
differential DAC output balances the A
charges. The SAR contents (a 16-bit data word) which
represent the difference of A
the 16-bit output latches.
DIGITAL INTERFACE
The A/D converter is designed to interface with micropro-
cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a con-
version.
Internal Clock
The A/D converter has an internal clock that runs the A/D
conversion. The internal clock is factory trimmed to achieve
a typical conversion time of 2.45 s and a maximum
conversion time of 2.8 s over the full temperature range.
No external adjustments are required. The guaranteed
maximum acquisition time is 480ns. In addition, a through-
put time (acquisition + conversion) of 3 s and a minimum
sampling rate of 333ksps are guaranteed.
3V Input/Output Compatible
The LTC1604 operates on 5V supplies, which makes the
device easy to interface to 5V digital systems. This device
can also talk to 3V digital systems: the digital input pins
(SHDN, CS, CONVST and RD) of the LTC1604 recognize
3V or 5V inputs. The LTC1604 has a dedicated output
supply pin (OV
digital output pins (D0 to D15, BUSY) and allows the part
to talk to either 3V or 5V digital systems. The output is
two’s complement binary.
Power Shutdown
The LTC1604 provides two power shutdown modes, Nap
and Sleep, to save power during inactive periods. The Nap
mode reduces the power by 95% and leaves only the
digital logic and reference powered up. The wake-up time
from Nap to active is 200ns. In Sleep mode all bias
DD
) that controls the output swings of the
IN
+
and A
IN
IN
–
+
are loaded into
and A
IN
–
input