AD7853LARSZ Analog Devices Inc, AD7853LARSZ Datasheet - Page 9

• Manufacturer Part Number: AD7853LARSZ
• Description: IC ADC 12BIT SRL 200KSPS 24SSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7853LARSZ

• Data Interface: 8051, QSPI™, Serial, SPI™ µP
• Number Of Bits: 12
• Sampling Rate (per Second): 100k
• Number Of Converters: 2
• Power Dissipation (max): 33mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP (0.200", 5.30mm Width)
• Resolution (bits): 12bit
• Sampling Rate: 100kSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 3V To 5.5V
• Supply Voltage Range - Digital: 3V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. B
ON-CHIP REGISTERS
The AD7853/AD7853L powers up with a set of default conditions, and the user need not ever write to the device. In this case the
AD7853/AD7853L will operate as a Read-Only ADC. The AD7853/AD7853L still retains the flexibility for performing a full power-
down, and a full self-calibration. Note that the DIN pin should be tied to DGND for operating the AD7853/AD7853L as a Read-
Only ADC.
Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali-
bration, and software conversion start can be selected by writing to the part.
The AD7853/AD7853L contains a Control register, ADC output data register, Status register, Test register and 10 Calibra-
tion registers. The control register is write-only, the ADC output data register and the status register are read-only, and the test and
calibration registers are both read/write registers. The test register is used for testing the part and should not be written to.
Addressing the On-Chip Registers
Writing
A write operation to the AD7853/AD7853L consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine
which register is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are writ-
ten that the data is latched into the addressed register. Table I shows the decoding of the address bits, while Figure 4 shows the over-
all write register hierarchy.
ADDR1
0
0
1
1
Reading
To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register.
Once the read selection bits are set in the control register all subsequent read operations that follow will be from the selected register
until the read selection bits are changed in the control register.
RDSLT1
0
0
1
1
Figure 4. Write Register Hierarchy/Address Decoding
CALSLT1, CALSLT0
DECODE
RDSLT0
0
1
0
1
ADDR0
0
1
0
1
OFFSET(1)
REGISTER
GAIN(1)
DAC(8)
00
01
TEST
Comment
This combination does not address any register so the subsequent 14 data bits are ignored.
This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test register.
This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are written
to the selected calibration register.
This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written to the
control register.
Comment
All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-up
default setting. There will always be four leading zeros when reading from the ADC output data register.
All successive read operations will be from TEST REGISTER.
All successive read operations will be from CALIBRATION REGISTERS.
All successive read operations will be from STATUS REGISTER.
OFFSET(1)
GAIN(1)
01
ADDR1, ADDR0
CALIBRATION
REGISTERS
DECODE
10
OFFSET(1)
10
Table II. Read Register Addressing
Table I. Write Register Addressing
REGISTER
CONTROL
GAIN(1)
11
11
–9–
Figure 5. Read Register Hierarchy/Address Decoding
CALSLT1, CALSLT0
DATA REGISTER
ADC OUTPUT
DECODE
00
OFFSET(1)
GAIN(1)
REGISTER
DAC(8)
00
01
TEST
OFFSET(1)
AD7853/AD7853L
GAIN(1)
01
RDSLT1, RDSLT0
CALIBRATION
REGISTERS
DECODE
10
OFFSET(1)
10
REGISTER
STATUS
GAIN(1)
11
11