AD7492ARZ Analog Devices Inc, AD7492ARZ Datasheet - Page 10

• Manufacturer Part Number: AD7492ARZ
• Description: IC ADC 12BIT W/REF W/CLK 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7492ARZ

• Data Interface: Parallel
• Number Of Bits: 12
• Sampling Rate (per Second): 1.25M
• Number Of Converters: 1
• Power Dissipation (max): 16.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Resolution (bits): 12bit
• Input Channel Type: Single Ended
• Supply Voltage Range - Analogue: 2.7V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Supply Current: 3mA
• Sampling Rate: 1MSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7492CBZ - BOARD EVALUATION FOR AD7492
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7492
ADC TRANSFER FUNCTION
The output coding of the AD7492 is straight binary. The designed
code transitions occur at successive integer LSB values (i.e.,
1 LSB, 2 LSB, etc.). The LSB size is = 2.5/4096 for the AD7492.
The ideal transfer characteristic for the AD7492 is shown in
Figure 6.
AC ACQUISITION TIME
In ac applications it is recommended to always buffer analog
input signals. The source impedance of the drive circuitry must
be kept as low as possible to minimize the acquisition time of
the ADC. Large values of impedance at the V
ADC will cause the THD to degrade at high input frequencies.
Input
Buffers
AD9631
AD797
DC Acquisition Time
The ADC starts a new acquisition phase at the end of a conver-
sion and ends it on the falling edge of the CONVST signal. At
the end of conversion there is a settling time associated with the
sampling circuit. This settling time lasts 120 ns. The analog
signal on V
therefore, the minimum acquisition time needed is 120 ns.
C/ P
Table I. Dynamic Performance Specifications
IN
2.5V
111...111
111...110
111...000
011...111
000...010
000...001
000...000
SNR
500 kHz
69.5
69.6
is also being acquired during this settling time;
PARALLELED
INTERFACE
0V 1/2LSB
1nF
100nF
THD
500 kHz
80
81.6
10 F
V
DV
REF OUT
DB0–
DB9 (DB11)
CS
CONVST
RD
BUSY
DRIVE
ANALOG INPUT
DD
AD7492
+
1LSB = V
AV
+V
DD
REF
PS/FS
V
–1LSB
0.1 F
IN
Current
17 mA
8.2 mA
Typical Amplifier
Consumption
REF
/4096
IN
+
0V TO 2.5V
pin of the
47 F
ANALOG
SUPPLY
2.7V–5.25V
Figure 7 shows the equivalent charging circuit for the sampling
capacitor when the ADC is in its acquisition phase. R3 represents
the source impedance of a buffer amplifier or resistive network,
R1 is an internal switch resistance, R2 is for bandwidth control,
and C1 is the sampling capacitor. C2 is back-plate capacitance
and switch parasitic capacitance.
During the acquisition phase the sampling capacitor must be
charged to within 0.5 LSB of its final value.
ANALOG INPUT
Figure 8 shows the equivalent circuit of the analog input struc-
ture of the AD7492. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. The capacitor C3 is typically
about 4 pF and can be primarily attributed to pin capacitance.
The resistor R1 is an internal switch resistance. This resistor is
typically about 125 Ω. The capacitor C1 is the sampling capaci-
tor while R2 is used for bandwidth control.
PARALLEL INTERFACE
The parallel interface of the AD7492 is 12 bits wide. The output
data buffers are activated when both CS and RD are logic low.
At this point the contents of the data register are placed onto the
data bus. Figure 9 shows the timing diagram for the parallel port.
Figure 10 shows the timing diagram for the parallel port when
CS and RD are tied permanently low. In this setup, once the
BUSY line goes from high to low, the conversion process is
completed. The data is available on the output bus slightly
before the falling edge of BUSY.
It is important to point out that the data bus cannot change
state while the A/D is doing a conversion as this would have a
detrimental effect on the conversion in progress. The data out
lines will go three-state again when either the RD or CS line
goes high. Thus the CS can be tied low permanently, leaving the
RD line to control conversion result access. Please reference the
V
OPERATING MODES
The AD7492 has two possible modes of operation depending on
the state of the CONVST pulse at the end of a conversion, Mode 1
and Mode 2.
Mode 1 (High-Speed Sampling)
In this mode of operation the CONVST pulse is brought high
before the end of conversion, i.e., before the BUSY goes low (see
Figure 10). If the CONVST pin is brought from high to low while
BUSY is high, the conversion is restarted. When operating in
DRIVE
section for output voltage levels.
V
IN
R3
4pF
C3
V
DD
V
D1
D2
IN
125
125
R1
R1
8pF
8pF
C2
C2
22pF
22pF
C1
C1
636
R2
636
R2