AD7492ARZ Analog Devices Inc, AD7492ARZ Datasheet - Page 4

• Manufacturer Part Number: AD7492ARZ
• Description: IC ADC 12BIT W/REF W/CLK 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7492ARZ

• Data Interface: Parallel
• Number Of Bits: 12
• Sampling Rate (per Second): 1.25M
• Number Of Converters: 1
• Power Dissipation (max): 16.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Resolution (bits): 12bit
• Input Channel Type: Single Ended
• Supply Voltage Range - Analogue: 2.7V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Supply Current: 3mA
• Sampling Rate: 1MSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7492CBZ - BOARD EVALUATION FOR AD7492
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7492
TIMING SPECIFICATIONS
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
5
Specifications subject to change without notice.
CONVERT
WAKEUP
1
2
3
4
5
6
7
8
9
10
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
Figure 1.
The AD7492-5 is specified with V
This is the time needed for the part to settle within 0.5 LSB of its stable value. Conversion can be initiated earlier than 20 µs, but we cannot guarantee that the part
will sample within 0.5 LSB of the true analog input value. Therefore we recommend that the user does not start conversion until after the specified time.
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
t
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
7
4
4
5
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
AD7492
880
20
500
10
10
40
0
0
20
15
8
0
120
100
3
DD
Limit at T
= 4.75 V to 5.25 V.
1
MIN
(V
DD
, T
= 2.7 V to 5.25 V, T
AD7492-5
680
20
500
10
10
N/A
0
0
20
15
8
0
120
100
MAX
TO OUTPUT
3
PIN
2
50pF
C
L
A
= T
Unit
ns max
µs max
µs max
ns min
ns max
ns max
ns max
ns max
ns min
ns min
ns max
ns max
ns min
ns min
200 A
200 A
MIN
to T
I
I
MAX
OL
OH
, unless otherwise noted.)
1.6V
Description
Partial Sleep Wake-Up Time
Full Sleep Wake-Up Time
CONVST Pulsewidth
CONVST to BUSY Delay, V
CONVST to BUSY Delay, V
BUSY to CS Setup Time
CS to RD Setup Time
RD Pulsewidth
Data Access Time after Falling Edge of RD
Bus Relinquish Time after Rising Edge of RD
CS to RD Hold Time
Acquisition Time
Quiet Time
7
, quoted in the timing characteristics is the true bus relinquish
DD
) and timed from a voltage level of 1.6 V. See
DD
DD
= 5 V
= 3 V